公开(公告)号：US20130009164A1

公开(公告)日：2013-01-10

申请号：US13353990

申请日：2012-01-19

Applicant: Jae Hoon Lee

Inventor： Jae Hoon Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0615 ,  H01L29/1058 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.

Abstract translation: 提供电力设备。 功率器件可以包括对应于栅电极图案的部分中的二维电子气（2-DEG）层，因为在形成第一氮化物层之后在栅电极图案的下部还形成第二氮化物层 因此，能够进行常关动作。 因此，功率器件可以基于栅极的电压来调整2-DEG层的产生，并且可以降低功耗。 功率器件可以只再生对应于栅极电极图案的部分，或者可以蚀刻除了与栅电极图案对应的部分之外的部分，因此凹陷处理可以是不允许的，可以确保功率器件的再现性，并且 制造过程可以被简化。

公开(公告)号：US20120280233A1

公开(公告)日：2012-11-08

申请号：US13226108

申请日：2011-09-06

Applicant: Jae Hoon LEE ,  Ki Se Kim

Inventor： Jae Hoon LEE ,  Ki Se Kim

IPC: H01L29/165

CPC classification number: H01L29/7787 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/872

Abstract: A high efficiency heterostructure field effect transistor (HFET) capable of suppressing a leakage current and enhancing a current density by lowering a barrier between an electrode and a semiconductor layer is provided. The high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (SixC1-x) functional layer formed on the AlGaN layer.

Abstract translation: 提供了能够通过降低电极和半导体层之间的阻挡层来抑制漏电流并提高电流密度的高效异质结构场效应晶体管（HFET）。 高效HFET可以包括基板，形成在基板上的半绝缘氮化镓（GaN）层，形成在GaN层上的氮化镓铝（AlGaN）层，以及形成的碳化硅（SixC1-x）功能层 在AlGaN层上。

公开(公告)号：US08301346B2

公开(公告)日：2012-10-30

申请号：US12409842

申请日：2009-03-24

Applicant: Jae Hoon Lee

Inventor： Jae Hoon Lee

IPC: G06F19/00

CPC classification number: F16H61/431 ,  F16H61/4061 ,  F16H61/4148 ,  F16H61/421

Abstract: A traveling system for construction equipment is provided, which can secure an initial traveling manipulability regardless of a low-speed traveling or a high-speed traveling. If the high-speed traveling is selected and the traveling is manipulated, the inclination angle of a swash plate of a hydraulic pump is variably controlled, so that the discharge flow rate of the hydraulic pump exceeds a predetermined flow rate in comparison to the low-speed traveling.

Abstract translation: 提供了一种用于施工设备的行驶系统，无论低速行驶还是高速行驶，都能确保初始的行驶操纵性。 如果选择高速行驶并且行驶被操纵，则液压泵的斜盘的倾斜角度被可变地控制，使得液压泵的排出流量与低速行驶相比， 速度旅行。

公开(公告)号：US20120212401A1

公开(公告)日：2012-08-23

申请号：US13242379

申请日：2011-09-23

Applicant: Yu-Han BAE ,  Jae-Hoon LEE ,  Seung-Hwan MOON

Inventor： Yu-Han BAE ,  Jae-Hoon LEE ,  Seung-Hwan MOON

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0465 ,  G09G2310/02 ,  G09G2310/0243 ,  G09G2310/0251 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2320/0223

Abstract: A display panel includes a display area, a peripheral area which includes a first peripheral area, and a second peripheral area opposite to the first peripheral area, a plurality of pixels in the display area, a plurality of data lines, a first gate line, a second gate line, a first gate driving circuit and a second gate driving circuit. Each data line corresponds to two pixel columns. The first gate line is at a first side of a pixel row. The second gate line is at a second side of the pixel row. The first gate driving circuit is in the first peripheral area and includes a first stage which provides a gate signal to the first gate line. The second gate driving circuit is in a second peripheral area of the display area and includes a second stage which provides a gate signal to the second gate line.

Abstract translation: 显示面板包括显示区域，包括第一外围区域的外围区域和与第一外围区域相反的第二外围区域，显示区域中的多个像素，多个数据线，第一栅极线， 第二栅极线，第一栅极驱动电路和第二栅极驱动电路。 每个数据线对应于两个像素列。 第一个栅极线位于像素行的第一侧。 第二栅极线位于像素行的第二侧。 第一栅极驱动电路在第一周边区域中，并且包括向第一栅极线提供栅极信号的第一级。 第二栅极驱动电路在显示区域的第二周边区域中，并且包括向第二栅极线提供栅极信号的第二级。

公开(公告)号：US20120182478A1

公开(公告)日：2012-07-19

申请号：US13428802

申请日：2012-03-23

Applicant: Jae-Hoon LEE

Inventor： Jae-Hoon LEE

IPC: H04N5/445

CPC classification number: H04R5/02 ,  H04R5/04

Abstract: An audio/video (A/V) device having a volume control function for external audio reproduction units by using volume control buttons of a remote controller is provided. The A/V device includes speakers, an audio output port for externally outputting an audio signal, an audio signal processing unit for reproducing and amplifying the audio signal and applying the amplified audio signal to the speakers or the audio output port, a memory unit for storing volume control values, and a control unit for applying to the audio signal processing unit any of the volume control values stored in the memory based on whether the external audio reproduction unit is plugged in the audio output port. The control unit controls the audio signal processing unit to adjust the volume control values for the audio output port by the volume control buttons when the external audio reproduction unit is plugged in the audio output port.

Abstract translation: 提供了通过使用遥控器的音量控制按钮，具有用于外部音频再现单元的音量控制功能的音频/视频（A / V）设备。 A / V装置包括扬声器，用于外部输出音频信号的音频输出端口，用于再现和放大音频信号并将放大的音频信号施加到扬声器或音频输出端口的音频信号处理单元，用于 存储音量控制值，以及控制单元，用于基于外部音频再现单元是否插入音频输出端口，将存储在存储器中的任何音量控制值应用于音频信号处理单元。 当外部音频再现单元插入音频输出端口时，控制单元控制音频信号处理单元，以通过音量控制按钮调节音频输出端口的音量控制值。

公开(公告)号：US20120162522A1

公开(公告)日：2012-06-28

申请号：US13411401

申请日：2012-03-02

Applicant: Jae-hoon LEE

Inventor： Jae-hoon LEE

IPC: H04N5/60 ,  H04N5/50

CPC classification number: H04R5/02 ,  H04R5/04

Abstract: An audio/video (A/V) device having a volume control function for external audio reproduction units by using volume control buttons of a remote controller is provided. The A/V device includes speakers, an audio output port for externally outputting an audio signal, an audio signal processing unit for reproducing and amplifying the audio signal and applying the amplified audio signal to the speakers or the audio output port, a memory unit for storing volume control values, and a control unit for applying to the audio signal processing unit any of the volume control values stored in the memory based on whether the external audio reproduction unit is plugged in the audio output port. The control unit controls the audio signal processing unit to adjust the volume control values for the audio output port by the volume control buttons when the external audio reproduction unit is plugged in the audio output port.

公开(公告)号：US20120146985A1

公开(公告)日：2012-06-14

申请号：US13180749

申请日：2011-07-12

Applicant: Whee-Won LEE ,  Seung-Hwan MOON ,  Jae-Hoon LEE ,  Jun-Yong SONG

Inventor： Whee-Won LEE ,  Seung-Hwan MOON ,  Jae-Hoon LEE ,  Jun-Yong SONG

IPC: G09G5/00 ,  G09G3/10

CPC classification number: G09G3/3696 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0281

Abstract: A method of driving a display panel includes generating a gate on voltage, generating first and second gate off voltages based on an external voltage in a first operating mode, and first and second gate off voltages based on the gate on voltage in a second operating mode, generating a clock signal based on the gate on voltage and the second gate off voltage and outputting a gate voltage generated based on the clock signal and the first and second gate off voltages to a gate line of the display panel.

Abstract translation: 驱动显示面板的方法包括：产生栅极导通电压，基于第一操作模式中的外部电压产生第一和第二栅极截止电压，以及基于第二工作模式中的栅极导通电压的第一和第二栅极截止电压 基于栅极导通电压和第二栅极截止电压产生时钟信号，并将基于时钟信号和第一和第二栅极截止电压产生的栅极电压输出到显示面板的栅极线。

公开(公告)号：US20120061727A1

公开(公告)日：2012-03-15

申请号：US13224482

申请日：2011-09-02

Applicant: Jae-hoon LEE ,  Ki-se Kim

Inventor： Jae-hoon LEE ,  Ki-se Kim

IPC: H01L29/778 ,  H01L21/335 ,  H01L21/329 ,  H01L29/872

CPC classification number: H01L23/373 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/3738 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/13 ,  H01L2924/12032 ,  H01L2924/00

Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.

Abstract translation: 基于氮化镓（GaN）的半导体器件及其制造方法。 GaN基半导体器件可以包括布置在散热衬底上的异质结构场效应晶体管（HFET）或肖特基二极管。 HFET器件可以包括具有凹陷区域的GaN基多层; 设置在所述凹部区域中的栅极; 以及布置在栅极（或凹部区域）的两个相对侧的GaN基多层的部分上的源极和漏极。 栅极，源极和漏极可以附接到散热基板。 凹部区域可以具有双凹槽结构。 虽然正在制造这种GaN基半导体器件，但是可以使用晶片接合工艺和激光剥离工艺。

公开(公告)号：US07991604B2

公开(公告)日：2011-08-02

申请号：US11888535

申请日：2007-08-01

Applicant: Jae-Hoon Lee

Inventor： Jae-Hoon Lee

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/62 ,  G06F2217/66 ,  G06F2217/84

Abstract: A method and an apparatus for indirectly simulating a semiconductor integrated circuit (IC) are described. A circle chain is formed using input pins and output pins to provide an intellectual property (IP) core model that substitutes for a real IP core circuit. A test bench for the IP core model is generated, the semiconductor IC that includes the IP core model is integrated using the generated test bench, and the semiconductor IC is simulated.

Abstract translation: 描述用于间接模拟半导体集成电路（IC）的方法和装置。 使用输入引脚和输出引脚形成环形链，以提供替代真实IP核心电路的知识产权（IP）核心模型。 生成IP核心模型的测试台，使用生成的测试台集成了包含IP核模型的半导体IC，模拟半导体IC。

公开(公告)号：US20110110127A1

公开(公告)日：2011-05-12

申请号：US12674618

申请日：2008-08-22

Applicant: Jae Hoon Lee

Inventor： Jae Hoon Lee

IPC: H02M1/42

CPC classification number: G05F1/70

Abstract: The present invention relates to a power factor correction circuit that can reduce distortion of input current in a switching mode power supply. The power factor correction circuit provided in the present invention basically comprises a first inductor which is electrically connected at a first end thereof to an input terminal, a second coil that is coupled to the first inductor to form an induced voltage, a switch electrically connected to the a second terminal of the first inductor, and a switching control unit for controlling turn-on and turn-off of the switch. In such a power factor correction circuit of the present invention, the switching control unit is configured to differently set a turn-on period of the switch depending on the input voltage by generating a signal for controlling the turn-off of the switch using a second coil voltage induced at the secondary coil of the inductor by input voltage or a directly sensed input voltage. Accordingly, distortion of input current can be effectively corrected.

Abstract translation: 本发明涉及能够减少开关模式电源中的输入电流的失真的功率因数校正电路。 本发明提供的功率因数校正电路基本上包括：第一电感器，其第一端电连接到输入端子;第二线圈，其耦合到第一电感器以形成感应电压，开关电连接到 第一电感器的第二端子和用于控制开关的接通和断开的开关控制单元。 在本发明的这种功率因数校正电路中，开关控制单元被配置为根据输入电压不同地设置开关的导通周期，通过产生用于控制开关的关断的信号，使用第二 通过输入电压或直接感应的输入电压在电感器的次级线圈感应的线圈电压。 因此，可以有效地校正输入电流的失真。