公开(公告)号：US08593444B2

公开(公告)日：2013-11-26

申请号：US13180749

申请日：2011-07-12

Applicant: Whee-Won Lee ,  Seung-Hwan Moon ,  Jae-Hoon Lee ,  Jun-Yong Song

Inventor： Whee-Won Lee ,  Seung-Hwan Moon ,  Jae-Hoon Lee ,  Jun-Yong Song

IPC: G06F3/038

CPC classification number: G09G3/3696 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0281

Abstract: A method of driving a display panel includes generating a gate on voltage, generating first and second gate off voltages based on an external voltage in a first operating mode, and first and second gate off voltages based on the gate on voltage in a second operating mode, generating a clock signal based on the gate on voltage and the second gate off voltage and outputting a gate voltage generated based on the clock signal and the first and second gate off voltages to a gate line of the display panel.

Abstract translation: 驱动显示面板的方法包括：产生栅极导通电压，基于第一操作模式中的外部电压产生第一和第二栅极截止电压，以及基于第二工作模式中的栅极导通电压的第一和第二栅极截止电压 基于栅极导通电压和第二栅极截止电压产生时钟信号，并将基于时钟信号和第一和第二栅极截止电压产生的栅极电压输出到显示面板的栅极线。

公开(公告)号：US20100090992A1

公开(公告)日：2010-04-15

申请号：US12472902

申请日：2009-05-27

Applicant: Whee-won LEE

Inventor： Whee-won LEE

IPC: G09G5/00

CPC classification number: G09G3/3688 ,  G09G2310/08

Abstract: A data driving apparatus includes a horizontal synchronization start signal generation circuit and data driving circuit. The horizontal synchronization start signal generation circuit generates a horizontal synchronization start signal using image data signals. The data driving circuit samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal. The horizontal synchronization start signal generation circuit is disabled in response to the load signal.

Abstract translation: 数据驱动装置包括水平同步开始信号产生电路和数据驱动电路。 水平同步开始信号生成电路使用图像数据信号生成水平同步开始信号。 数据驱动电路响应于水平同步开始信号对图像数据信号进行采样，并且响应于负载信号使用采样图像数据信号提供多个数据信号。 水平同步开始信号产生电路响应于负载信号被禁用。

公开(公告)号：US20120146985A1

公开(公告)日：2012-06-14

申请号：US13180749

申请日：2011-07-12

Applicant: Whee-Won LEE ,  Seung-Hwan MOON ,  Jae-Hoon LEE ,  Jun-Yong SONG

Inventor： Whee-Won LEE ,  Seung-Hwan MOON ,  Jae-Hoon LEE ,  Jun-Yong SONG

IPC: G09G5/00 ,  G09G3/10

CPC classification number: G09G3/3696 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0281

Abstract: A method of driving a display panel includes generating a gate on voltage, generating first and second gate off voltages based on an external voltage in a first operating mode, and first and second gate off voltages based on the gate on voltage in a second operating mode, generating a clock signal based on the gate on voltage and the second gate off voltage and outputting a gate voltage generated based on the clock signal and the first and second gate off voltages to a gate line of the display panel.

Abstract translation: 驱动显示面板的方法包括：产生栅极导通电压，基于第一操作模式中的外部电压产生第一和第二栅极截止电压，以及基于第二工作模式中的栅极导通电压的第一和第二栅极截止电压 基于栅极导通电压和第二栅极截止电压产生时钟信号，并将基于时钟信号和第一和第二栅极截止电压产生的栅极电压输出到显示面板的栅极线。

公开(公告)号：US08957882B2

公开(公告)日：2015-02-17

申请号：US13292661

申请日：2011-11-09

Applicant: Jae-Hoon Lee ,  Young-Su Kim ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae ,  You-Mee Hyun

Inventor： Jae-Hoon Lee ,  Young-Su Kim ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae ,  You-Mee Hyun

IPC: G06F3/038 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/041 ,  G11C19/28

Abstract: A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.

Abstract translation: 栅极驱动电路包括其中多级级联连接的移位寄存器。 在第n级中，上拉部分响应于第一节点上的高电压，将时钟信号的高电压输出到输出节点作为第n栅极信号的高电压。 下拉部分响应于第（n + 1）个进位信号将第n个门信号的高电压降低到第一低电压。 放电部分响应于第（n + 1）个进位信号，将第一节点放电到比第一低电压电平低的第二低电压电平。 进位部分响应于第一节点上的高电压，输出时钟信号的高电压作为第n个进位信号（反映第n个门信号）。

公开(公告)号：US08542177B2

公开(公告)日：2013-09-24

申请号：US12472902

申请日：2009-05-27

Applicant: Whee-won Lee

Inventor： Whee-won Lee

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/08

Abstract: A data driving apparatus includes a horizontal synchronization start signal generation circuit and data driving circuit. The horizontal synchronization start signal generation circuit generates a horizontal synchronization start signal using image data signals. The data driving circuit samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal. The horizontal synchronization start signal generation circuit is disabled in response to the load signal.

Abstract translation: 数据驱动装置包括水平同步开始信号产生电路和数据驱动电路。 水平同步开始信号生成电路使用图像数据信号生成水平同步开始信号。 数据驱动电路响应于水平同步开始信号对图像数据信号进行采样，并且响应于负载信号使用采样图像数据信号提供多个数据信号。 水平同步开始信号产生电路响应于负载信号被禁用。

公开(公告)号：US20130135273A1

公开(公告)日：2013-05-30

申请号：US13460566

申请日：2012-04-30

Applicant: Whee-Won LEE ,  Jae Hoon LEE ,  Young-Su KIM

Inventor： Whee-Won LEE ,  Jae Hoon LEE ,  Young-Su KIM

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2320/041

Abstract: A liquid crystal display, including: pixels; a signal controller receiving an input image signal and an input control signal and outputting a processing image signal and a control signal; and a data driver changing the processing image signal to data voltage on the basis of the control signal to supply the data voltage to the pixel and sharing charges of odd channel data voltage of an odd channel and even channel data voltage of an even channel which have different polarities on the basis of a temperature.

Abstract translation: 液晶显示器，包括：像素; 信号控制器，接收输入图像信号和输入控制信号，并输出处理图像信号和控制信号; 数据驱动器基于控制信号将处理图像信号改变为数据电压，以将数据电压提供给像素，并且分配奇数通道的奇数通道数据电压和偶数通道的偶数通道数据电压的电荷， 基于温度的不同极性。

公开(公告)号：US09672782B2

公开(公告)日：2017-06-06

申请号：US12949931

申请日：2010-11-19

Applicant: Jae-Hoon Lee ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Young-Su Kim ,  Chang-Ho Lee ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae

Inventor： Jae-Hoon Lee ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Young-Su Kim ,  Chang-Ho Lee ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae

IPC: G09G3/36 ,  G11C19/00 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/28

Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

公开(公告)号：US09552891B2

公开(公告)日：2017-01-24

申请号：US13331360

申请日：2011-12-20

Applicant: Jae Hoon Lee ,  Whee-Won Lee

Inventor： Jae Hoon Lee ,  Whee-Won Lee

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286

Abstract: A display panel includes: gate and data lines; pixels connected to the gate and data lines; and a stage includes: a pull-up driver including an output terminal of the stage and which outputs a gate-on voltage, an output pull-down unit which pulls down an output terminal of the stage, a reset unit which changes a voltage of a second node into a low voltage based on a voltage of the output terminal of the stage, a first node pull-up unit which changes a first node into a high voltage based on a gate-on voltage from a previous stage, a first node pull-down unit which changes the first node into the low voltage based on the gate-on voltage from a subsequent stage, and a first node reset unit which changes the voltage of the first node into the low voltage based on the voltage of the second node.

Abstract translation: 显示面板包括：门和数据线; 连接到门和数据线的像素; 并且载台包括：上拉驱动器，其包括所述载波台的输出端子，并输出栅极导通电压;输出下拉单元，其拉低所述载波台的输出端子;复位单元， 基于所述级的输出端子的电压的第二节点变为低电压;第一节点上拉单元，其基于来自前一级的栅极导通电压将第一节点改变为高电压;第一节点 下拉单元，其基于来自后续级的栅极导通电压将第一节点改变为低电压;以及第一节点复位单元，其基于第二节点的电压将第一节点的电压改变为低电压 节点。

公开(公告)号：US20130027378A1

公开(公告)日：2013-01-31

申请号：US13331360

申请日：2011-12-20

Applicant: Jae Hoon LEE ,  Whee-Won LEE

Inventor： Jae Hoon LEE ,  Whee-Won LEE

IPC: G09G5/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286

Abstract: A display panel includes: gate and data lines; pixels connected to the gate and data lines; and a stage includes: a pull-up driver including an output terminal of the stage and which outputs a gate-on voltage, an output pull-down unit which pulls down an output terminal of the stage, a reset unit which changes a voltage of a second node into a low voltage based on a voltage of the output terminal of the stage, a first node pull-up unit which changes a first node into a high voltage based on a gate-on voltage from a previous stage, a first node pull-down unit which changes the first node into the low voltage based on the gate-on voltage from a subsequent stage, and a first node reset unit which changes the voltage of the first node into the low voltage based on the voltage of the second node.

Abstract translation: 显示面板包括：门和数据线; 连接到门和数据线的像素; 并且载台包括：上拉驱动器，其包括所述载波台的输出端子，并输出栅极导通电压;输出下拉单元，其拉低所述载波台的输出端子;复位单元， 基于所述级的输出端子的电压的第二节点变为低电压;第一节点上拉单元，其基于来自前一级的栅极导通电压将第一节点改变为高电压;第一节点 下拉单元，其基于来自后续级的栅极导通电压将第一节点改变为低电压;以及第一节点复位单元，其基于第二节点的电压将第一节点的电压改变为低电压 节点。

公开(公告)号：US20120139883A1

公开(公告)日：2012-06-07

申请号：US13292661

申请日：2011-11-09

Applicant: Jae-Hoon LEE ,  Young-Su KIM ,  Whee-Won LEE ,  Jun-Yong SONG ,  Yu-Han BAE ,  You-Mee HYUN

Inventor： Jae-Hoon LEE ,  Young-Su KIM ,  Whee-Won LEE ,  Jun-Yong SONG ,  Yu-Han BAE ,  You-Mee HYUN

IPC: G06F3/038 ,  H03K3/00

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/041 ,  G11C19/28

Abstract: A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.

Abstract translation: 栅极驱动电路包括其中多级级联连接的移位寄存器。 在第n级中，上拉部分响应于第一节点上的高电压，将时钟信号的高电压输出到输出节点作为第n栅极信号的高电压。 下拉部分响应于第（n + 1）个进位信号将第n个门信号的高电压降低到第一低电压。 放电部分响应于第（n + 1）个进位信号，将第一节点放电到比第一低电压电平低的第二低电压电平。 进位部分响应于第一节点上的高电压，输出时钟信号的高电压作为第n个进位信号（反映第n个门信号）。