公开(公告)号：US20070257744A1

公开(公告)日：2007-11-08

申请号：US11822652

申请日：2007-07-09

Applicant: Jan Westra ,  Jan Mulder ,  Franciscus van der Goes

Inventor： Jan Westra ,  Jan Mulder ,  Franciscus van der Goes

IPC: H03H7/24

CPC classification number: H03H11/245 ,  H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

公开(公告)号：US07262639B2

公开(公告)日：2007-08-28

申请号：US11038388

申请日：2005-01-21

Applicant: Jan Mulder ,  Franciscus Maria Leonardus van der Goes ,  Marcel Lugthart

Inventor： Jan Mulder ,  Franciscus Maria Leonardus van der Goes ,  Marcel Lugthart

IPC: H03K5/22

CPC classification number: G01R19/16519 ,  G01R19/16557 ,  H03K3/356139 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0604

Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.

Abstract translation: 差分比较器，具有更低的电源电压，具有改进的误码率性能。 差分比较器包括接收差分输入的第一对晶体管。 第二对晶体管耦合到第一对晶体管。 一对电阻元件连接在第一对和第二对晶体管之间，以增加由第一和第二对晶体管共享的偏置电流。 增加的偏置电流减少差分比较器从元稳定状态转变到稳定状态所需的时间，从而提高差分比较器的误码率。 电阻元件可以使用线性电阻或传输门。 第一或第二对晶体管的栅极可以提供输出。

公开(公告)号：US07129865B2

公开(公告)日：2006-10-31

申请号：US11087685

申请日：2005-03-24

Applicant: Jan Mulder ,  Franciscus M. L. van der Goes

Inventor： Jan Mulder ,  Franciscus M. L. van der Goes

IPC: H03M1/06

CPC classification number: H03M1/0863 ,  H03M1/36

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract translation: 一种用于减少具有比较器阵列的模数转换器中的位错误的方法。 第一和第二比较器的输出在异或门的输入中被接收。 第一和第二比较器由阵列中的第三比较器分开。 异或门的输出用于确定第三比较器是否处于亚稳态。 如果第三比较器处于亚稳态，则第三比较器的锁存电路的偏置电流增加，以增加第三比较器转变到稳定状态的速率。

公开(公告)号：US20060105725A1

公开(公告)日：2006-05-18

申请号：US10986020

申请日：2004-11-12

Applicant: Yee Cheung ,  Kevin Chan ,  Jan Mulder

Inventor： Yee Cheung ,  Kevin Chan ,  Jan Mulder

IPC: H03F1/14 ,  H04B1/04 ,  H01Q11/12

CPC classification number: H04B1/581

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The transmitter includes a plurality of current cells. Each cell is configurable for operating in different modes. The method includes determining a first probability associated with transmitting data at a particular symbolic level and determining a second probability associated with each cell being used during a transmission at the particular symbolic level. Next, one of the modes for each cell is selected in accordance with anticipated performance requirements. An average current of the transmitter is then calculated based upon the determined first and second probabilities and the selected modes.

公开(公告)号：US20050140446A1

公开(公告)日：2005-06-30

申请号：US11060395

申请日：2005-02-17

Applicant: Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

Inventor： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

IPC: H03H11/32 ,  H03F3/45

CPC classification number: H03H11/32

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

公开(公告)号：US20050109912A1

公开(公告)日：2005-05-26

申请号：US10716882

申请日：2003-11-20

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: F16B1/00 ,  F16F15/00 ,  F16F15/02 ,  F16M11/12 ,  H01Q1/00 ,  H01Q1/12 ,  F16M13/00

CPC classification number: F16M11/125 ,  F16F15/02 ,  F16F2230/0052 ,  F16M11/046 ,  F16M2200/041 ,  H01Q1/005 ,  H01Q1/1207

Abstract: This invention relates to elementary and complex coupling devices. In particular, such coupling devices may be used for supporting radar, antenna or optical sensor equipment, notably on vessels. The invention is an elementary coupling device comprising a means for stiffening the elementary coupling device against torsion. Means are provided for linking the stiffening means for stiffening to a second object to be coupled. First hinging means for hinging each linking means directly or indirectly on the second object to be coupled at two separate points. Two second hinging means for hinging the means for stiffening on each means for linking at two separate points. Hinging means for hinging the stiffening means are provided directly or indirectly on a first object to be coupled at two separate points. A complex coupling device comprising three of these elementary coupling devices.

Abstract translation: 本发明涉及基本和复杂耦合器件。 特别地，这种耦合装置可以用于支持雷达，天线或光学传感器设备，特别是在容器上。 本发明是一种基本耦合装置，其包括用于加强基本耦合装置以抵抗扭转的装置。 提供了用于将用于加强的加强装置连接到要耦合的第二物体的装置。 第一铰接装置，用于将每个连接装置直接地或间接地铰接在待耦合的第二物体上，在两个分开的点处。 两个第二铰链装置，用于在每个装置上铰接用于加强的装置，用于在两个分开的点连接。 用于铰接加强装置的铰接装置直接地或间接地设置在要在两个分开的点处联接的第一物体上。 一种复合耦合装置，包括这些基本耦合装置中的三个。

公开(公告)号：US06771127B2

公开(公告)日：2004-08-03

申请号：US10105253

申请日：2002-03-26

Applicant: Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

Inventor： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

IPC: H03F345

CPC classification number: H03H11/32

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

Abstract translation: 提供了在提供共模电压控制的同时执行单端到差分转换的电路。 电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。 稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。 比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。 调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。

公开(公告)号：US06727839B2

公开(公告)日：2004-04-27

申请号：US10226165

申请日：2002-08-23

Applicant: Jan Mulder ,  Franciscus M. L. van der Goes

Inventor： Jan Mulder ,  Franciscus M. L. van der Goes

IPC: H03M134

CPC classification number: H03M1/0863 ,  H03M1/36

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract translation: 一种用于减少具有比较器阵列的模数转换器中的位错误的方法。 第一和第二比较器的输出在异或门的输入中被接收。 第一和第二比较器由阵列中的第三比较器分开。 异或门的输出用于确定第三比较器是否处于亚稳态。 如果第三比较器处于亚稳态，则第三比较器的锁存电路的偏置电流增加，以增加第三比较器转变到稳定状态的速率。

公开(公告)号：US06720798B2

公开(公告)日：2004-04-13

申请号：US10158193

申请日：2002-05-31

Applicant: Jan Mulder ,  Yee Ling Cheung

Inventor： Jan Mulder ,  Yee Ling Cheung

IPC: H03K522

CPC classification number: H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/365 ,  H03M1/742 ,  H04L25/026 ,  H04L25/0276

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

公开(公告)号：US06674388B2

公开(公告)日：2004-01-06

申请号：US10349073

申请日：2003-01-23

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: H03M114

CPC classification number: H03M1/0863 ,  H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/36 ,  H03M1/365

Abstract: An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase &phgr;1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases &phgr;1 and &phgr;2, a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase &phgr;2 and substantially rejecting the output signal and the corresponding taps during the phase &phgr;1, and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.

Abstract translation: 模数转换器包括参考梯形图，跟踪和保持放大器，在相位phi1期间跟踪具有其输出信号的输入信号并保持采样值，粗略模数转换器具有多个粗放大器，每个粗放大器输入 来自参考梯形图和输出信号的对应抽头，具有多个精细放大器的精细模数转换器，该精细放大器从参考梯形图输入相应的抽头和输出信号，基于粗放大器的输出选择的抽头， 具有相位phi1和phi2的时钟，响应于接收输出信号的时钟的电路，电路在相位phi2期间基本上将输出信号和相应的抽头传递到精细放大器，并在该期间基本上拒绝输出信号和对应的抽头 相位phi1和将粗略和精细放大器的输出转换成表示th的N位数字信号的编码器 e输入信号。