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公开(公告)号：US12107590B2
公开(公告)日：2024-10-01
申请号：US18049278
申请日：2022-10-24
Inventor： Sharvil Pradeep Patil , Asha Ganesan , Hajime Shibata , Donald W. Paterson , Haiyang Zhu
CPC classification number: H03M1/0604 , H03M1/1038 , H03M1/1047 , H03M1/164
Abstract: Continuous-time (CT) analog-to-digital converters (ADCs) implementing digital correction of digital-to-analog converter (DAC) errors are disclosed. In a CT pipeline stage of a CT ADC, a CT analog input signal is sent to two different paths. A first path (a “feedforward” path) includes a cascade of a sub-ADC and a sub-DAC. A second path (a “forward” path) includes an analog delay circuit to align the delays of the input signal in the feedforward and forward paths. A combiner subtracts the output of the analog delay of the forward path from the output of the sub-DAC in the feedforward path to generate a residue signal. Devices and methods disclosed herein are based on recognition that, if the errors introduced by the sub-DAC are known, they can be corrected in the digital domain during reconstruction, achieving superior NSD and distortion performance compared to conventional approaches.
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公开(公告)号：US20240272589A1
公开(公告)日：2024-08-15
申请号：US18429541
申请日：2024-02-01
Applicant: ROHM CO., LTD.
Inventor： Keno SATO , Tamotsu ICHIKAWA , Takashi ISHIDA , Toshiyuki OKAMOTO , Takayuki NAKATANI , Haruo KOBAYASHI
CPC classification number: G04F10/005 , H03M1/0604
Abstract: A time-to-digital converter circuit that measures a time difference between a first input signal and a second input signal includes: a jitter superimposition circuit that superimposes a jitter, which changes temporally, on one of the first input signal and the second input signal to generate a first intermediate signal and a second intermediate signal; a time-to-digital converter that measures a time difference between the first intermediate signal and the second intermediate signal each time the jitter changes; and a statistical processor that statistically processes a plurality of time differences measured by the time-to-digital converter in response to a plurality of jitters, and calculates a time difference between the first input signal and the second input signal.
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公开(公告)号：US20240259027A1
公开(公告)日：2024-08-01
申请号：US18160741
申请日：2023-01-27
Applicant: VIAVI Solutions Inc.
Inventor： Pablo PEREZ LARA , John Wilson
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: In some implementations, a receiver may obtain a digitized output of a radio frequency (RF) analog-to-digital-converter (ADC) of the receiver. The receiver may apply a spur cancellation to the digitized output of the RF ADC to attenuate one or more continuous wave spurs from the digitized output of the RF ADC, wherein the spur cancellation is based on a frequency planning with coherent averaging.
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4.发明公开公开(公告)号：US20240213992A1
公开(公告)日：2024-06-27
申请号：US18145025
申请日：2022-12-22
Applicant: Intel Corporation
Inventor： Daniel GRUBER , Michael KALCHER , Martin CLARA
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: A digital-to-analog converter (DAC) and a method for correcting amplitude and/or skew error in a DAC. The DAC includes a main DAC, cell error determination circuit, a correction DAC, and a combiner. The main DAC includes a plurality of DAC cells. The cell error determination circuit is configured to determine an amplitude error and/or a skew error of each of the plurality of DAC cells and generate error data of the DAC based on the input data to the DAC cells. The correction DAC is configured to generate an error signal based on the error data. The combiner is configured to combine the error signal with an output of the main DAC.
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公开(公告)号：US11973510B2
公开(公告)日：2024-04-30
申请号：US17751900
申请日：2022-05-24
Inventor： Le Ye , Heyi Li , Ru Huang , Hao Zhang , Yuanxin Bao
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: Disclosed are a capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip. The capacitance-to-digital conversion circuit includes a first module, a comparator and an adaptive range-shift module; the first module includes a successive approximation unit, a first adder, a first digital-to-analog converter, a second adder, a third adder and an integrating unit. The first module further includes a second digital-to-analog converter connected to the third adder. The comparator, the adaptive range-shift module and the first adder are connected in series and the comparator is connected to the second digital-to-analog converter. By the present application, the adverse influence caused by the parasitic and interference is well avoided, the capacitance-to-digital conversion circuit may work in a harsh environment, the robustness of the circuit is significantly improved and the application range of the circuit is expanded.
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Patent Agency Ranking
公开(公告)号：US11962316B2
公开(公告)日：2024-04-16
申请号：US17451234
申请日：2021-10-18
Applicant: Infineon Technologies AG
Inventor： Luis Hernandez , Ruben Garvi Jimenez-Ortiz , Andreas Wiesbauer
CPC classification number: H03M1/0604 , H03M1/0614 , H03M1/60 , H04R2201/003
Abstract: An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.
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公开(公告)号：US20240097690A1
公开(公告)日：2024-03-21
申请号：US18227027
申请日：2023-07-27
Inventor： Murat Demirkan , Michael E. Harrell , Dennis A. Dempsey , Zahit Evren Kaya
CPC classification number: H03M1/0604 , H03F3/04
Abstract: A method of feedback control of an amplifier system includes driving multiple amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set a system output of the amplifier system, operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady state target output, detecting a high glitch transition of the first set of DAC codes that is greater than a specified threshold transition, and changing to operating the at least one DAC circuit using a second set of DAC codes to set the system output to substantially the same steady state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the at least one DAC circuit.
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公开(公告)号：US11936395B2
公开(公告)日：2024-03-19
申请号：US17586179
申请日：2022-01-27
Applicant: Texas Instruments Incorporated
Inventor： Tanmay Neema , Gautam Salil Nandi , Rishubh Khurana , Atul Kumar Agrawal , Deepak Kumar Meher
CPC classification number: H03M1/0604 , H03M1/1057 , H03M1/687 , H03M1/785 , H03M1/808 , H03M1/66
Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.
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公开(公告)号：US20240072816A1
公开(公告)日：2024-02-29
申请号：US17990737
申请日：2022-11-21
Inventor： Ting-Hao Wang , Hui-Wen Tsai , Shih-Chun Lo
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.
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公开(公告)号：US20240039548A1
公开(公告)日：2024-02-01
申请号：US18206623
申请日：2023-06-07
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Sun , Chuan-Hung Hsiao , Sung-Han Wen
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: A digital-to-analog converter (DAC) includes a plurality of DAC cells, a mismatch error sorting circuit, and a dynamic element matching (DEM) circuit. The mismatch error sorting circuit generates a sorting result of the plurality of DAC cells according to mismatch error levels of the plurality of DAC cells. The DEM circuit shapes the mismatch error levels of the plurality of DAC cells according to the sorting result of the plurality of DAC cells.
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