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    Satellite constellations
    72.
    发明授权
    Satellite constellations 有权

    公开(公告)号：US11479372B2

    公开(公告)日：2022-10-25

    申请号：US17102324

    申请日：2020-11-23

    Applicant: Space Exploration Technologies Corp.

    Inventor： Jonathan F. C. Herman ,  Stephen Mance ,  Paul A. Forquera ,  Mark Krebs

    IPC: B64G1/10 ,  B64G3/00

    Abstract: A method of communication with a non-GEO constellation of satellites, includes providing an Earth-based terminal configured for communication with a satellite constellation, and establishing communication between the Earth-based terminal and a non-GEO constellation of satellites, the non-GEO constellation of satellites including a first plurality of satellites orbiting at a first inclination, wherein each of the satellites in the first plurality of satellites is in a discrete planar orbit to form a first snake of satellites, the first snake of satellites including adjacent satellites in adjacent orbits having adjacent RAAN (Right Ascension of the Ascending Node), wherein the Earth-based terminal is positioned and configured for continuous communication with at least one satellite from the non-GEO constellation of satellites.

    BEAMFORMER LATTICE FOR PHASED ARRAY ANTENNAS
    78.
    发明申请
    BEAMFORMER LATTICE FOR PHASED ARRAY ANTENNAS 有权

    公开(公告)号：US20220069887A1

    公开(公告)日：2022-03-03

    申请号：US17471098

    申请日：2021-09-09

    Applicant: Space Exploration Technologies Corp.

    Inventor： Nil Apaydin ,  Chiara Pelletti ,  Souren Shamsinejad ,  Alireza Mahanfar

    IPC: H04B7/08 ,  H01Q21/06 ,  H04B7/06 ,  H01Q1/38 ,  H01Q21/22

    Abstract: In some embodiments, an apparatus includes a plurality of first conductive traces oriented in a first direction in a first layer and plurality of second conductive traces oriented in a second direction in a second layer coupled by vias to define first hierarchical networks. A plurality of third conductive traces oriented in the first direction in a third layer and a plurality of fourth conductive traces oriented in the second direction in a fourth layer are coupled by vias to define second hierarchical networks. Open ends of the first or second traces at a last stage of the first hierarchical networks comprise first ends and open ends of the third or fourth traces at a last stage of the second hierarchical networks comprise second ends. A first end and a corresponding second end are non-collinear to each other and perpendicular to a major plane of the first layer.

    Pre-deployment battery power conservation for spacecraft
    79.
    发明授权
    Pre-deployment battery power conservation for spacecraft 有权

    公开(公告)号：US11254451B2

    公开(公告)日：2022-02-22

    申请号：US15930415

    申请日：2020-05-12

    Applicant: Space Exploration Technologies Corp.

    Inventor： Mohammed Faraz Admani ,  Pieter Buysschaert ,  Andrew D. Roberts ,  Garrett P. Simard

    IPC: B64G1/42 ,  B64G1/00 ,  B64G1/66

    Abstract: Embodiments of the present disclosure are directed to techniques for autonomously transitioning a spacecraft from a power-saving state to a power-consuming state at a time after launch of the spacecraft on a launch vehicle. Because the spacecraft can autonomously detect conditions for transitioning to the power-consuming state, commands received via an umbilical connection to the launch vehicle, or detecting the presence or absence of such a connection, is unnecessary, thereby removing several technical barriers to eliminating such umbilical connections altogether. In some embodiments, low-cost vacuum detection devices that use very small amounts of power may be used by the spacecraft to detect when the spacecraft has reached an altitude suitable for transitioning to the power-consuming state.

    CHIP TO CHIP TIME SYNCHRONIZATION
    80.
    发明申请
    CHIP TO CHIP TIME SYNCHRONIZATION 有权

    公开(公告)号：US20220006610A1

    公开(公告)日：2022-01-06

    申请号：US17478599

    申请日：2021-09-17

    Applicant: Space Exploration Technologies Corp.

    Inventor： Andras Tantos ,  David Francois Jacquet ,  Mario Toma

    IPC: H04L7/033

    Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

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