公开(公告)号：US07037776B2

公开(公告)日：2006-05-02

申请号：US10323981

申请日：2002-12-19

Applicant: Jenn-Ming Huang ,  Chen-Yong Lin

Inventor： Jenn-Ming Huang ,  Chen-Yong Lin

IPC: H01L21/8242

CPC classification number: H01L27/1104 ,  H01L27/10861 ,  H01L27/11

Abstract: A method of fabricating a DRAM cell, comprising the following steps. A substrate is provided. An isolation structure is formed within the substrate. The substrate is patterned to form nodes adjacent the isolation structure. Doped regions are formed with the substrate adjacent the nodes. A gate dielectric layer is formed over the patterned substrate, lining the nodes. A conductive layer is formed over the gate dielectric layer, filling the nodes. The conductive layer is patterned to form: a top electrode capacitor within the nodes; and respective word lines over the substrate adjacent the top electrode capacitor; each word line having exposed side walls. Source/drain regions are formed adjacent the word lines.

Abstract translation: 一种制造DRAM单元的方法，包括以下步骤。 提供基板。 在衬底内形成隔离结构。 将衬底图案化以形成邻近隔离结构的节点。 掺杂区域与衬底相邻的节点形成。 栅极电介质层形成在图案化衬底上，衬在节点上。 导电层形成在栅介质层上，填充节点。 将导电层图案化以形成：节点内的顶部电极电容器; 以及邻近顶部电极电容器的衬底上的各个字线; 每个字线具有暴露的侧壁。 源极/漏极区域形成在字线附近。

公开(公告)号：US06338998B1

公开(公告)日：2002-01-15

申请号：US09713652

申请日：2000-11-15

Applicant: Chen-Jong Wang ,  Chen-Yong Lin ,  Kevin Chiang

Inventor： Chen-Jong Wang ,  Chen-Yong Lin ,  Kevin Chiang

IPC: H01L218242

CPC classification number: H01L27/10894 ,  H01L27/10811 ,  H01L27/10873

Abstract: Within a method for fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication there is formed contacting a second source/drain region within a field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication device a storage capacitor prior to forming within a field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device a pair of first source/drain regions. By employing such a process ordering, the field effect transistor (FET) logic semiconductor integrated circuit microelectronic device, and the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication, are fabricated with enhanced performance.

Abstract translation: 在用于制造嵌入式动态随机存取存储器（DRAM）半导体集成电路微电子制造的方法中，形成在场效应晶体管（FET）存储器半导体集成电路微电子制造器件中的第二源极/漏极区域之前形成的存储电容器 在场效应晶体管（FET）逻辑半导体集成电路微电子制造装置内有一对第一源/漏区。 通过采用这种处理顺序，以增强的性能制造场效应晶体管（FET）逻辑半导体集成电路微电子器件以及嵌入式动态随机存取存储器（DRAM）半导体集成电路微电子制造。