Pixel structure and method for driving the same, display panel and display apparatus

    公开(公告)号:US11114005B2

    公开(公告)日:2021-09-07

    申请号:US16623989

    申请日:2019-07-23

    IPC分类号: G09G3/20

    摘要: A pixel structure is disclosed. The pixel structure includes: a plurality of scanning lines; a plurality of data lines intersecting the plurality of scanning lines; and a plurality of sub-pixels which are located at respective intersections of the plurality of scanning lines and the plurality of data lines and are arranged in rows and columns. (4n+1)th and (4n+2)th data lines of the plurality of data lines are located on opposite sides of a (2n+1)th column of sub-pixels respectively. (4n+3)th and (4n+4)th data lines of the plurality of data lines are located on opposite sides of a (2n+2)th column of sub-pixels respectively. The (4n+2)th and (4n+3)th data lines of the plurality of data lines are located between the (2n+1)th column of sub-pixels and the (2n+2)th column of sub-pixels, where n is an integer greater than or equal to 0.

    SHIFT REGISTER AND TIME-SHARING CONTROLLING METHOD THEREOF, DISPLAY PANEL AND DISPLAY APPARATUS

    公开(公告)号:US20190164497A1

    公开(公告)日:2019-05-30

    申请号:US15980985

    申请日:2018-05-16

    发明人: Li Wang

    IPC分类号: G09G3/3266 G11C19/28

    摘要: Embodiments of the application provide a shift register comprising a shift signal generating circuit and at least two time-sharing controlling circuits. The shift signal generating circuit may be configured to generate a shift signal. Each of the time-sharing controlling circuits comprises a first driving sub-circuit and a second driving sub-circuit, wherein the first driving sub-circuit is configured to enable the time-sharing controlling circuit to output the shift signal during the preset period, and the second driving sub-circuit is configured to enable the time-sharing controlling circuit to output an invalid signal during the non-preset period. During a driving cycle, the first driving sub-circuits in each of the at least two time-sharing controlling circuits are turned on sequentially, so that each of the at least two time-dividing controlling circuits outputs the shift signal sequentially.

    Display panel and manufacturing method thereof, and display device

    公开(公告)号:US11997892B2

    公开(公告)日:2024-05-28

    申请号:US17279689

    申请日:2020-06-18

    摘要: Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a plurality of sub-pixels, each sub-pixel including a light-emitting element and a pixel driving circuit; a plurality of gate lines and light-emitting control lines; a gate driving circuit located at the display area and including cascaded multistage gate driving units, one or more stages include gate driving sub-circuits including a first and a second gate driving sub-circuit spaced apart by pixel driving circuits of a first group of sub-pixels; and a light-emitting control driving circuit located at the display area and including cascaded multistage light-emitting control driving units, one or more stages include light-emitting control driving sub-circuits including a first and a second light-emitting control driving sub-circuit spaced apart by pixel driving circuits of a second group of sub-pixels.

    Display panel having level signal wiring patterns

    公开(公告)号:US11430855B2

    公开(公告)日:2022-08-30

    申请号:US17003872

    申请日:2020-08-26

    发明人: Li Wang

    摘要: The present disclosure provides a display panel and a method for manufacturing the display panel. The display panel includes: a base substrate; a conductive layer on the base substrate including a level signal wiring pattern; a cathode layer on a side of the conductive layer away from the base substrate; an anode layer on the side of the conductive layer away from the base substrate and on a side of the cathode layer facing the base substrate; a thin film transistor on a side of the anode layer facing the base substrate and on the side of the conductive layer away from the base substrate, including a source electrode, a drain electrode, an active layer, and a gate electrode, wherein the level signal wiring pattern is electrically connected to the cathode layer.

    Display Panel and Manufacturing Method Thereof, and Display Device

    公开(公告)号:US20220199737A1

    公开(公告)日:2022-06-23

    申请号:US17279689

    申请日:2020-06-18

    IPC分类号: H01L27/32 G09G3/3225

    摘要: Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a plurality of sub-pixels, each sub-pixel including a light-emitting element and a pixel driving circuit; a plurality of gate lines and light-emitting control lines; a gate driving circuit located at the display area and including cascaded multistage gate driving units, one or more stages include gate driving sub-circuits including a first and a second gate driving sub-circuit spaced apart by pixel driving circuits of a first group of sub-pixels; and a light-emitting control driving circuit located at the display area and including cascaded multistage light-emitting control driving units, one or more stages include light-emitting control driving sub-circuits including a first and a second light-emitting control driving sub-circuit spaced apart by pixel driving circuits of a second group of sub-pixels.

    Display Panel and Manufacturing Method Thereof, and Display Device

    公开(公告)号:US20220199736A1

    公开(公告)日:2022-06-23

    申请号:US17279636

    申请日:2020-06-18

    摘要: Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes: a base substrate including a display area and a peripheral area including a first peripheral area, and an edge of the first peripheral area is of a first curvature greater than zero; a plurality of sub-pixels, data lines and gate lines; a gate driving circuit located at the display area and including multistage gate driving units, one or more stages include a first and a second gate driving sub circuit; a plurality of control signal lines, at least a part of at least one control signal line is of a second curvature greater than zero; a plurality of data signal input lines; and a multiplexing circuit including a plurality of multiplexing units, each of which is connected to the control signal lines, one data signal input line, and at least two data lines.