公开(公告)号：US5313207A

公开(公告)日：1994-05-17

申请号：US71497

申请日：1993-06-04

申请人： Hiroyuki Kouno ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Hiroyuki Kouno ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03F3/45 ,  G06G7/14 ,  H03F3/72 ,  H03M1/14 ,  H03M1/34 ,  H03M1/36 ,  H03M1/12

CPC分类号： H03M1/164 ,  G06G7/14 ,  H03F3/72

摘要： An improved differential subtracter 3a and an improved D/A converter 7a are used in a two-step parallel A/D converter 100. The D/A converter is responsive to complementary signals S1-S2 and B1-Bn indicative of results of conversion of higher bits to draw subtraction currents Is1 and Is2 through emitter electrodes of npn transistors Q1 and Q2. Since a difference between emitter currents I.sub.E1 and I.sub.E2 is small, base-emitter voltages V.sub.BE1 and V.sub.BE2 are substantially equal to each other. As a result, the A/D converter can execute the subtraction at high speed with high accuracy.

摘要翻译： 改进的差分减法器3a和改进的D / A转换器7a用于两级并行A / D转换器100.D / A转换器响应于指示转换结果的互补信号S1-S2和B1-Bn 较高位以通过npn晶体管Q1和Q2的发射极来减去电流Is1和Is2。 由于发射极电流IE1和IE2之间的差异小，所以基极 - 发射极电压VBE1和VBE2基本相等。 因此，A / D转换器可以高精度地执行减法。

公开(公告)号：US5148164A

公开(公告)日：1992-09-15

申请号：US685411

申请日：1991-04-16

申请人： Yasuyuki Nakamura ,  Toshio Kumamoto

发明人： Yasuyuki Nakamura ,  Toshio Kumamoto

IPC分类号： H03K17/041

CPC分类号： H03K17/04106

摘要： A current generating device for generating two different currents having different magnitudes in response to corresponding one-bit data of digital data of a plurality of bits includes: NMOS transistors, (1,2,3), a control signal generating circuit and a supply circuit. The control signal generating circuit generates a voltage (V2) at which NMOS transistors (2,3) can be turned on and a voltage (V3) which is in the range between a ground potential and threshold values of the NMOS transistors and at which NMOS transistors (2,3) can be turned off. The supply circuit complementarily applies voltages (V1,V2) to NMOS transistors (2,3). NMOS transistor (1) generates a current with a predetermined magnitude. NMOS transistors (2,3) respond to voltages (V2, V3) to switch and allow/prevent passage of the predetermined-magnitude current generated by NMOS transistor (1).

摘要翻译： 电流产生装置，用于响应于多个位的数字数据的对应的一位数据而产生具有不同幅度的两个不同电流，包括：NMOS晶体管，（1,2,3），控制信号发生电路和电源电路 。 控制信号发生电路产生NMOS晶体管（2,3）可以导通的电压（V2）和位于NMOS晶体管的接地电位和阈值之间的范围内的电压（V3），NMOS 晶体管（2,3）可以关闭。 电源电路互补地将电压（V1，V2）施加到NMOS晶体管（2,3）。 NMOS晶体管（1）产生具有预定大小的电流。 NMOS晶体管（2,3）响应于电压（V2，V3）来切换并允许/阻止由NMOS晶体管（1）产生的预定电流的通过。

公开(公告)号：US4695748A

公开(公告)日：1987-09-22

申请号：US900442

申请日：1986-08-26

申请人： Toshio Kumamoto

发明人： Toshio Kumamoto

IPC分类号： H03K5/08 ,  H03K5/24

CPC分类号： H03K5/249

摘要： A comparing device comprises a first CMOS inverter (6) for detecting a difference between a voltage to be compared (Vin) and a reference voltage (Vref), a second CMOS inverter (9) connected directly to the first CMOS inverter (6) and a third CMOS inverter (11) connected directly to the second CMOS inverter (9), the input of the first CMOS inverter (6) and the output of the third CMOS inverter (11) being connected through a transmission gate (22). The current-driven capacity of the first CMOS inverter (6) is selected to be larger than that of the second inverter (9) and that of the third inverter (11) so that the difference between the voltage to be compared (Vin) and the reference voltage (Vref) can be detected precisely at high speed. The second inverter (9) and the third inverter (11) have a desired voltage amplifying function so that the voltage difference detected by the first inverter (6) can be amplified by these two inverters (9 and 11) and either of the binary outputs can be obtained at an output terminal (12).

摘要翻译： 比较装置包括用于检测要比较的电压（Vin）和参考电压（Vref）之间的差的第一CMOS反相器（6），直接连接到第一CMOS反相器（6）的第二CMOS反相器（9）和 与第二CMOS反相器（9）直接连接的第三CMOS反相器（11），通过传输门（22）连接第一CMOS反相器（6）的输入端和第三CMOS反相器（11）的输出端。 选择第一CMOS反相器（6）的电流驱动容量大于第二反相器（9）和第三反相器（11）的电流驱动容量，使得要比较的电压（Vin）和 可以高速精确检测参考电压（Vref）。 第二反相器（9）和第三反相器（11）具有期望的电压放大功能，使得由第一反相器（6）检测的电压差可以由这两个反相器（9和11）和二进制输出 可以在输出端子（12）处获得。