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71.发明申请公开(公告)号：US20090309770A1
公开(公告)日：2009-12-17
申请号：US12138920
申请日：2008-06-13
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
IPC分类号： H03M7/00
CPC分类号： H03M13/296 , H03M13/2725 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6569
摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.
摘要翻译： 提供了用于多种代码类型的可编程解码的方法和装置。 提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。 识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。 可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。 还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。 使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。 通过将数据写入到通信网络的目标地址来交织数据。 通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。
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72.发明授权公开(公告)号：US07584442B2
公开(公告)日：2009-09-01
申请号：US11298894
申请日：2005-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译： 提供了一种用于创建和使用存储器定时数据库的方法和装置。 定义了多个表征存储器，其可被映射到存储器资源。 每个表征存储器具有不同的存储器参数。 还定义了将每个表征存储器平铺到存储器资源的多种变型。 每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。
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公开(公告)号：US20090133003A1
公开(公告)日：2009-05-21
申请号：US11944104
申请日：2007-11-21
IPC分类号： G06F9/45
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译： 提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。 该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。 处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。
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公开(公告)号：US20080049719A1
公开(公告)日：2008-02-28
申请号：US11924385
申请日：2007-10-25
IPC分类号： H04L13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入端的位的值，以直接或转置的顺序向两个输出提供两个输入端的信号。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
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75.发明申请Method and apparatus for mapping design memories to integrated circuit layout 失效将设计存储器映射到集成电路布局的方法和装置公开(公告)号：US20070113212A1
公开(公告)日：2007-05-17
申请号：US11280110
申请日：2005-11-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译： 提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。 预置位模型与列表中的每个命名存储器类型相关联。 列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。 映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。 然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。
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公开(公告)号：US20070044053A1
公开(公告)日：2007-02-22
申请号：US11205365
申请日：2005-08-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译： 一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播 恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。 该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。 特别地，RRAM是这样的网表。
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77.发明授权FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作公开(公告)号：US07181563B2
公开(公告)日：2007-02-20
申请号：US10692664
申请日：2003-10-23
IPC分类号： G06F12/00
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译： 本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。 在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块 的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求 时钟周期。
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公开(公告)号：US07111264B2
公开(公告)日：2006-09-19
申请号：US10688460
申请日：2003-10-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译： 通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。 通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别 。
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79.发明授权公开(公告)号：US07096413B2
公开(公告)日：2006-08-22
申请号：US10299270
申请日：2002-11-19
CPC分类号： H03M13/6505 , H03M13/27 , H03M13/2957 , H03M13/6566
摘要： A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.
摘要翻译： 用于存储在n个存储器中的访问数据的解码器包括在唯一坐标处包含存储器位置的地址的函数矩阵。 分解器从第一和第二m×n矩阵的坐标位置排序地址，使得每行包含来自同一存储器的不超过一个地址。 位置装置存储识别功能矩阵中地址的坐标的第三和第四m×n矩阵中的条目，使得第三矩阵中的每个条目在与第一矩阵中的对应坐标匹配的坐标处，并且第四矩阵中的每个条目在匹配的坐标处 第二个矩阵中的对应坐标。 解码器响应于矩阵中的条目，用于从存储器并行访问数据。
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公开(公告)号：US07003510B2
公开(公告)日：2006-02-21
申请号：US10177591
申请日：2002-06-19
CPC分类号： G06F17/5045 , Y10S707/99933
摘要： A method of constructing a circuit for a Boolean function includes receiving as input a Boolean function of a number n of input variables wherein the number n of input variables may be varied over a range; generating at least two intermediate functions comprising sub-functions of the Boolean function wherein zero or one is substituted for all but two of the number n of input variables; and generating a selected output of the Boolean function of the number n of input variables from only two of the intermediate functions.
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