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公开(公告)号：US20070143648A1
公开(公告)日：2007-06-21
申请号：US11311388
申请日：2005-12-19
IPC分类号： G11C29/00
CPC分类号： G11C5/04
摘要： A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.
摘要翻译： 提供了存储器定时模型，其包括地址输入，多位数据输入，多位数据输出，容量C和宽度N.N个1位宽存储器模块彼此并行地实例化 数据输入的各个位和数据输出。 每个存储器模块具有通过地址输入寻址的C位的容量。
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公开(公告)号：US06587990B1
公开(公告)日：2003-07-01
申请号：US09678201
申请日：2000-10-01
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.
摘要翻译： 本发明是一种优化组合电路设计的方法和装置。 该方法包括为组合电路构建电路束，然后进行矢量优化。 在优选实施例中，确定完整的BDD B，并且从中计算出F组的列表。 如果组合电路包括除NOT，AND和XOR单元以外的单元，则首先对电路进行转换，使其仅具有这些类型的单元。
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公开(公告)号：US20050050426A1
公开(公告)日：2005-03-03
申请号：US10648038
申请日：2003-08-26
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由多路复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
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公开(公告)号：US06536016B1
公开(公告)日：2003-03-18
申请号：US09626037
申请日：2000-07-27
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, and the second mathematical representation is a function of the operation of the first logical cell and a function of the second variable. A determination is then made as to whether one of the first and second mathematical representations is equal to a constant.
摘要翻译： 在组合电路中通过将组合电路的输入与第一变量和第二变量相关联来确定恒定引脚，第二变量是第一变量的补码。 对于与这种输入互连的第一逻辑单元，计算第一数学表示和第二数学表示。 第一数学表示是第一逻辑单元的操作和第一变量的函数的函数，第二数学表示是第一逻辑单元的操作和第二变量的函数的函数。 然后确定第一和第二数学表示中的一个是否等于常数。
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5.发明授权公开(公告)号：US06530063B1
公开(公告)日：2003-03-04
申请号：US09677276
申请日：2000-10-02
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.
摘要翻译： 本发明涉及一种用于确定组合电路中恒定引脚的方法。 该方法包括以下步骤：将组合电路的输入与第一变量和第二变量相关联，其中所述第二变量是所述第一变量的补码，对于与所述输入互连的第一逻辑单元计算第一规范表示，其中 所述第一规范表示是所述第一逻辑单元的操作和所述第一值的函数的函数，对于所述第一逻辑单元计算第二规范表示，其中所述第二规范表示是所述第一逻辑单元的操作的函数 以及所述第二值的函数，确定所述第一和第二规范表示中的一个是否等于零。
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公开(公告)号：US20080049719A1
公开(公告)日：2008-02-28
申请号：US11924385
申请日：2007-10-25
IPC分类号： H04L13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入端的位的值，以直接或转置的顺序向两个输出提供两个输入端的信号。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
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7.发明申请FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作公开(公告)号：US20050091465A1
公开(公告)日：2005-04-28
申请号：US10692664
申请日：2003-10-23
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译： 本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。 在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块 的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求 时钟周期。
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8.发明授权Method and apparatus for minimization of net delay by optimal buffer insertion 有权通过最佳缓冲区插入最小化净延迟的方法和装置公开(公告)号：US06519746B1
公开(公告)日：2003-02-11
申请号：US09685990
申请日：2000-10-10
IPC分类号： G06F945
CPC分类号： G06F17/505
摘要： The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.
摘要翻译： 本发明涉及一种减少网络延迟的方法。 该方法包括构建时空网格，所述时间网格对应于网络，将波通过时空网格，所述波具有波值，并在所述时空网格上的点处插入缓冲器 其中缓冲器的插入增加波值。 缓冲区可以是负缓冲区或正缓冲区。 通常，第二波与第一波同时通过时空网格。 通常，第二波和第一波反转。
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公开(公告)号：US20080046764A1
公开(公告)日：2008-02-21
申请号：US11620794
申请日：2007-01-08
IPC分类号： G06F12/14
CPC分类号： G06F21/6218
摘要： A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.
摘要翻译： 一种通过产生随机化值来存储敏感数据的方法，将敏感数据和随机化值变换为结果，并将结果的分离部分存储在至少两个存储设备上，使得如果敏感数据中的任何一个 存储设备受到损害。
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10.发明申请Method and BIST architecture for fast memory testing in platform-based integrated circuit 有权方法和BIST架构，用于基于平台的集成电路中的快速内存测试公开(公告)号：US20060156088A1
公开(公告)日：2006-07-13
申请号：US10999493
申请日：2004-11-30
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/26 , G11C2029/2602
摘要： The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
摘要翻译： 本发明提供了一种用于基于平台的集成电路中的快速存储器测试的方法和BIST架构。 该方法可以包括以下步骤。 启动Mem-BIST控制器发送器，使用确定性和无条件测试算法为平台中的存储器生成输入信号。 输入信号被第一组管道延迟了n个时钟周期。 延迟的输入信号由存储器接收，并且由存储器产生输出信号。 输出信号被第二个流水线延迟了m个时钟周期。 启动Mem-BIST控制器接收器以接收延迟的输出信号进行比较。
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