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公开(公告)号：US20240329883A1
公开(公告)日：2024-10-03
申请号：US18610155
申请日：2024-03-19
Applicant: Micron Technology, Inc.
Inventor： Saideep Tiku , Poorna Kale
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0683
Abstract: A memory sub-system operable to balance the performance goals of different types of applications. For example, first requests generated by a first type of applications running in a host system to access a storage medium of a memory sub-system can be identified and placed in a first queue. Second requests generated by a second type of applications running in the host system to access the storage medium of the memory sub-system can be identified and placed in a second queue. Servicing to the first queue and the second queue can be interleaved according to the performance requirement (e.g., based on throughput in storage access) of the first type of applications and the performance requirement (e.g., based on latency in storage access) of the second type of applications.
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公开(公告)号：US20240329841A1
公开(公告)日：2024-10-03
申请号：US18607266
申请日：2024-03-15
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Poorna Kale
CPC classification number: G06F3/0611 , G06F3/0659 , G06F3/0679 , G06N20/00
Abstract: Methods, systems, and devices for analog computing configured memory are described. A memory system may implement a non-volatile memory array that includes a first portion of memory cells configured for storing data, and a second portion of memory cells configured to perform analog computing operations associated with a machine learning operation. The memory system may include supporting circuitry for receiving and storing data to the first portion, and transferring the data stored in the first portion to the second portion for use in the analog computing operations without transferring the data to a memory system controller. The memory system may include computing circuitry configured to generate data for the machine learning operation based on the outputs of the analog computing operations performed at the second portion. The computing circuitry may store the generated data to the first portion or transmit the generated data to the memory system controller.
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公开(公告)号：US20240289634A1
公开(公告)日：2024-08-29
申请号：US18439217
申请日：2024-02-12
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Pavana Prakash , Poorna Kale
Abstract: Apparatuses and methods related to federated learning are described. A host system can, responsive to a valid trust signal from a first local device, communicate a global model and a global loss value to the local device. The host system can receive a local loss value from the local device. The local loss value can be based on execution of a local version of the global model, generated by the local device, on a local test dataset by the local device. The host system can analyze the local loss value based on quantities of training samples and test samples. Responsive to the local loss value being more preferred than the global loss value, the host system can receive the local version of the global model from the local device, update the global model, and communicate the updated global model to the local device and to another local device.
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公开(公告)号：US20240282106A1
公开(公告)日：2024-08-22
申请号：US18415018
申请日：2024-01-17
Applicant: Micron Technology, Inc.
Inventor： Saideep Tiku , Poorna Kale
CPC classification number: G06V20/20 , G06F3/147 , G06V10/74 , G06V10/82 , G06V20/53 , G06V40/168 , G06V40/173 , G06V40/174 , G06V40/20
Abstract: An augment reality security system to identify outliers in behaviors. For example, cameras can be each configured to capture images, compress the images, and provide compressed images having embeddings representative of features determined by an artificial neural network. A server computer can receive, from the plurality of cameras, compressed images to generate analytics of embeddings of features in the compressed images, identify from the analytics an anomaly associated with a first face, and determine metrics representative of features of the first face in an image. A pair of augmented reality glasses can have a computing unit to detect a second face in a view through the glasses, communicate with the server computer to determine a match of the second face with the first face based on the metrics, and generate an augmented reality display in the view to identify the first face.
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公开(公告)号：US20240281291A1
公开(公告)日：2024-08-22
申请号：US18414842
申请日：2024-01-17
Applicant: Micron Technology, Inc.
Inventor： Saideep Tiku , Febin Sunny , Shashank Bangalore Lakshman , Poorna Kale
CPC classification number: G06F9/5033 , G06F9/4881 , G06F15/80
Abstract: An apparatus having a plurality of accelerators of different types for operations of multiplication and accumulation. In response to a request to perform a task of multiplication and accumulation on input data, the apparatus can analyze the input data to determine characteristics of the input data. The characteristics are indicative of energy efficiency levels of the accelerators in performing the task. The apparatus can assign the task to one of the accelerators based on the characteristics for improved energy efficiency, in addition to balancing workloads for the accelerators. For example, the different types of accelerators can include accelerators configured to perform multiplication and accumulation using microring resonators, synapse memory cells, logical multiply-accumulate units, memristors, etc.
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Patent Agency Ranking
公开(公告)号：US20240281210A1
公开(公告)日：2024-08-22
申请号：US18415301
申请日：2024-01-17
Applicant: Micron Technology, Inc.
Inventor： Saideep Tiku , Poorna Kale
CPC classification number: G06F7/5443 , G06F17/16
Abstract: An apparatus to compute an attention matrix implementing an attention mechanism in artificial neural networks, having: a plurality of memory regions; and a controller configured to receive key value pairs of an attention model, identify a plurality of subsets of the key value pairs to store the plurality of subsets in the plurality of memory regions respectively, and refresh the plurality of memory regions at a plurality of refreshing rates according to representative zero-to-one bit ratios of keys and values stored in the plurality of subsets.
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公开(公告)号：US20240202521A1
公开(公告)日：2024-06-20
申请号：US18535926
申请日：2023-12-11
Applicant: Micron Technology, Inc.
Inventor： Pavana Prakash , Shashank Bangalore Lakshman , Febin Sunny , Saideep Tiku , Poorna Kale
IPC: G06N3/08
CPC classification number: G06N3/08
Abstract: Training the ANN can include providing an initial ANN model to a plurality of groups of edge devices and providing an input to a group of edge devices from the plurality of groups of edge devices. Training the ANN can also include, responsive to providing the input, receiving activation signals from a first portion of the plurality of groups. Training the ANN can include providing the activation signals to a second portion of the plurality of groups and provide commands to the plurality of groups of edge devices to train the initial ANN model to generate a trained ANN model based on training feedback generated using different activation signals received from the second portion of the plurality of groups. Training the ANN can also include receiving the trained ANN model from the plurality of groups of edge devices.
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公开(公告)号：US20240171192A1
公开(公告)日：2024-05-23
申请号：US18501664
申请日：2023-11-03
Applicant: Micron Technology, Inc.
Inventor： Febin Sunny , Saideep Tiku , Shashank Bangalore Lakshman , Poorna Kale
Abstract: A device having: memory cells configured to store a set of first parameters as an input for an operation of multiplication and accumulation; digital to analog converters; an analog section of the operation of multiplication and accumulation; analog to digital converters; and a controller configured to analyze the set of first parameters to identify an encoding parameter for reduced energy consumption in processing the input. The device generates, using the digital to analog converters and according to the set of first parameters, analog inputs to the analog section of the operation of multiplication and accumulation. The analog section generates analog outputs responsive to the analog input. The device determines, using the analog to digital converters and according to the encoding parameter and the analog outputs, a set of second parameters as an output responsive to the input for the operation of multiplication and accumulation.
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公开(公告)号：US20240161246A1
公开(公告)日：2024-05-16
申请号：US18491582
申请日：2023-10-20
Applicant: Micron Technology, Inc.
Inventor： Saideep Tiku , Poorna Kale
CPC classification number: G06T5/50 , G06T3/40 , G06T9/00 , G06T2207/20221
Abstract: A method to generate a series of previews of an image with low latency, includes: retrieving, from a storage device in a first pass, first portions of image data representative of an image; generating, based on the first portions and without at least second portions of the image data, a first preview of the image; presenting the first preview; retrieving, from the storage device in a second pass, the second portions of the image data; generating, based on the first portions and the second portions of the image data, a second preview of the image; and presenting the second preview.
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公开(公告)号：US20240160738A1
公开(公告)日：2024-05-16
申请号：US18487677
申请日：2023-10-16
Applicant: Micron Technology, Inc.
Inventor： Saideep Tiku , Poorna Kale
IPC: G06F21/56 , B60W50/14 , G06N3/0442
CPC classification number: G06F21/566 , B60W50/14 , G06N3/0442 , G06F2221/034
Abstract: A device to detect attacks on a memory system in an advanced driver-assistance system (ADAS) of a vehicle. The device has an interface operable on a memory channel, a random access memory, a non-volatile memory cell array, and a controller configured to detect a trigger event, and in response: identify a sequence of commands received in the interface from the memory channel to access memory services provided via at least the random access memory during ADAS operations; perform operations of multiplication and accumulation using the non-volatile memory cell array to implement computations of an artificial neural network responsive to the sequence of commands as an input to generate a classification of the sequence as an output; and provide the classification via the interface.
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