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公开(公告)号：US20240378456A1
公开(公告)日：2024-11-14
申请号：US18658041
申请日：2024-05-08
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Pavana Prakash , Poorna Kale
IPC: G06N3/098
Abstract: Authentication based secure federated learning can be beneficial when updates to an initial artificial neural network (ANN) model generated by edge devices are to be aggregated into a federated ANN model. The updates can be generated by the edge devices after training the initial ANN locally. The edge devices can encrypt the updates using edge device-specific identifiers and transmit the encrypted updates to a server. The server can verify the authenticity of the updates, decrypt the updates, and aggregate the updates into the federated ANN model. The aggregation can be performed according to a secure multiparty computation protocol.
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公开(公告)号：US20240367670A1
公开(公告)日：2024-11-07
申请号：US18640865
申请日：2024-04-19
Applicant: Micron Technology, Inc.
Inventor： Pavana Prakash , Shashank Bangalore Lakshman , Febin Sunny , Saideep Tiku , Poorna Kale
Abstract: The present disclosure includes apparatuses, methods, and systems for displaying output data from a driver attention model on a display. In an example, an apparatus can include a sensor, an augmented reality (AR) windshield, a memory, and a processor coupled to the memory, the sensor, and the AR windshield, wherein the processor is configured to receive an initial driver attention model, train the initial driver attention model to create a trained driver attention model, transmit the trained driver attention model, receive a global driver attention model based in part on the trained driver attention model, receive sensor data based on operation of the apparatus, run the global driver attention model on the sensor data to generate output data, and cause the output data to be displayed on the AR windshield.
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公开(公告)号：US20240346328A1
公开(公告)日：2024-10-17
申请号：US18624754
申请日：2024-04-02
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Pavana Prakash , Poorna Kale
Abstract: Network video recorders (NVRs) can be configured to receive video data from operation in a location, train an artificial neural network (ANN) surveillance model with the video data, and provide updates to the ANN surveillance model to a server. The server can be configured to aggregate the updates into a federated ANN surveillance model. The server can deploy the federated ANN surveillance model to the NVRs. The server can train, via transfer learning based on the federated ANN surveillance model, a different ANN surveillance model for a different NVR in a different location. The server can deploy the different ANN surveillance model to the different NVR.
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公开(公告)号：US20230187010A1
公开(公告)日：2023-06-15
申请号：US18084892
申请日：2022-12-20
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman
CPC classification number: G11C29/50004 , G11C11/221 , G11C11/2275 , G11C11/2259 , G11C11/2273 , G11C11/2293 , G11C2029/5004
Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US20210090681A1
公开(公告)日：2021-03-25
申请号：US16580972
申请日：2019-09-24
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman
Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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Patent Agency Ranking
公开(公告)号：US12190947B2
公开(公告)日：2025-01-07
申请号：US17562598
申请日：2021-12-27
Applicant: Micron Technology, Inc.
Inventor： Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman , Jonathan D. Harms
Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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7.发明公开公开(公告)号：US20240282071A1
公开(公告)日：2024-08-22
申请号：US18415474
申请日：2024-01-17
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Saideep Tiku , Poorna Kale
CPC classification number: G06V10/235 , G06T7/0004 , H04N25/79 , G06T2207/20081 , G06T2207/20084
Abstract: Customization of a deep neural network model to analyze different regions of an image at different machine vision acuity levels. A graphical user interface presents an image captured by an image sensing pixel array and receives user interactions with the image to define regions of the machine vision acuity levels. Based on the user interactions with the graphical user interface, a region mask is generated to identify the regions of pixels in the image sensing pixel array. According to the region mask, unnecessary computations of low machine vision acuity are removed from the deep neural network model to generate a customized computing model of analyzing image data, captured by the image sensing pixel array, at the machine vision acuity levels.
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公开(公告)号：US20240280813A1
公开(公告)日：2024-08-22
申请号：US18415256
申请日：2024-01-17
Applicant: Micron Technology, Inc.
Inventor： Saideep Tiku , Shashank Bangalore Lakshman , Poorna Kale
CPC classification number: G02B27/017 , G02B27/0101 , G06T19/006 , G06V10/82 , G02B2027/0178
Abstract: An augmented reality device having a pair of glasses and an artificial neural network partially implemented via a passive neural network and partially implemented via digital circuits. The passive neural network can process image lights representative of a scene in a view of the pair of glasses to generate a light pattern. An array of light sensing pixels can convert the light pattern into data representative of outputs of a first set of artificial neurons of the artificial neural network. A processor can execute instructions to perform computations of a second set of artificial neurons of the artificial neural network responsive to the outputs of the first set of artificial neurons. A digital accelerator can accelerate multiplication and accumulation operations applied on weight matrices of the second set of artificial neurons.
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公开(公告)号：US12040038B2
公开(公告)日：2024-07-16
申请号：US18084892
申请日：2022-12-20
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman
CPC classification number: G11C29/50004 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C2029/5004
Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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10.发明公开公开(公告)号：US20240231993A1
公开(公告)日：2024-07-11
申请号：US18405793
申请日：2024-01-05
Applicant: Micron Technology, Inc.
Inventor： Pavana Prakash , Shashank Bangalore Lakshman , Febin Sunny , Saideep Tiku , Poorna Kale
IPC: G06F11/07
CPC classification number: G06F11/079 , G06F11/0709
Abstract: The present disclosure includes apparatuses, methods, and systems for classifying an area as hazardous or non-hazardous based on an operation of a semiconductor device. In an example, an apparatus can include a memory configured to store a global operation model and a processor coupled to the memory wherein the processor is configured to receive test data and operating data from a semiconductor device based on operation of the semiconductor device in an area, run the global operation model on the test data and the operating data from the semiconductor device to generate output data, and classify the area as hazardous or non-hazardous based on the output data.
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