公开(公告)号：US11935824B2

公开(公告)日：2024-03-19

申请号：US17665749

申请日：2022-02-07

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Julius Kovats

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L25/0652

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

公开(公告)号：US11824079B2

公开(公告)日：2023-11-21

申请号：US17233285

申请日：2021-04-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01C7/00 ,  H01L21/768 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01L21/76807 ,  H01L23/53238

Abstract: A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a conductive path between the pair of TFR heads through the TFR element, and TFR contacts connected to the TFR heads. The TFR heads may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The TFR element may be formed by depositing and patterning a TFR element/diffusion barrier layer over the TFR heads and interconnect elements formed in the metal interconnect layer. The TFR element may be formed from a material that also provides a barrier against metal diffusion (e.g., copper diffusion) from each metal TFR head and interconnect element. For example, the TFR element may be formed from tantalum nitride (TaN).

公开(公告)号：US20230361159A1

公开(公告)日：2023-11-09

申请号：US17834065

申请日：2022-06-07

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02 ,  H01C7/00 ,  H01L27/01 ,  H01L23/522 ,  H01L21/768 ,  H01C17/075

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01L27/016 ,  H01L23/5228 ,  H01L21/76816 ,  H01L21/76843 ,  H01C17/075

Abstract: A thin film resistor (TFR) module includes a metal cup structure, a dielectric liner region, a TFR element, and a pair of TFR heads electrically connected to the TFR element. The metal cup structure includes a laterally-extending metal cup base and multiple metal cup sidewalls extending upwardly from the laterally-extending metal cup base. The dielectric liner region is formed in an opening defined by the metal cup structure. The TFR element is formed in an opening defined by the dielectric liner region, wherein the TFR element is insulated from the metal cup structure by the dielectric liner region.

公开(公告)号：US20230352398A1

公开(公告)日：2023-11-02

申请号：US18218197

申请日：2023-07-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/528 ,  H01L21/67 ,  H01L21/66 ,  H01L23/522

CPC classification number: H01L23/5223 ,  H01L21/67259 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/40

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

公开(公告)号：US11769793B2

公开(公告)日：2023-09-26

申请号：US17516141

申请日：2021-11-01

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L28/92 ,  H01L21/7687 ,  H01L23/5223 ,  H01L23/5226

Abstract: A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.

公开(公告)号：US20230268380A1

公开(公告)日：2023-08-24

申请号：US17749367

申请日：2022-05-20

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.

公开(公告)号：US20230129684A1

公开(公告)日：2023-04-27

申请号：US17719548

申请日：2022-04-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01F17/00 ,  H01L49/02 ,  H01L23/532 ,  H01F27/28 ,  H01L23/528

Abstract: A device includes (a) an integrated inductor having an inductor wire and (b) a metal interconnect arrangement, both formed in an integrated circuit layer stack of alternating metal layers and via layers. At least a portion of the inductor wire is defined by an inductor element stack including multiple metal layer inductor elements formed in multiple respective metal layers, and multiple via layer inductor elements formed in multiple respective via layers and conductively connected to the metal layer inductor elements. Each via layer inductor element has a length of at least 1 μm in each of two lateral directions orthogonal to each other and perpendicular to the vertical direction. The metal interconnect arrangement includes metal layer interconnect elements formed in the respective metal layers, and interconnect vias formed in the respective via layers.

公开(公告)号：US20230128990A1

公开(公告)日：2023-04-27

申请号：US17719586

申请日：2022-04-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01F17/00 ,  H01L49/02 ,  H01L21/768

Abstract: A device includes an integrated inductor and metal interconnect formed in an integrated circuit (IC) structure. The integrated inductor includes an inductor wire having a portion defined by an inductor element stack including (a) a metal layer inductor element formed in a metal layer in the IC structure and (b) a multi-component via layer inductor element formed in a via layer in the IC structure vertically adjacent the metal layer, and conductively connected to the metal layer inductor element. The multi-component via layer inductor element includes a via layer inductor element cup-shaped component formed from a first metal, and a via layer inductor element fill component formed from a second metal in an opening defined by the via layer inductor element cup-shaped component. The metal interconnect includes a metal layer interconnect element formed in the metal layer, and an interconnect via formed in the via layer from the first metal.

公开(公告)号：US11626474B2

公开(公告)日：2023-04-11

申请号：US17170975

申请日：2021-02-09

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L49/02

Abstract: A thin film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a TFR element connected between first and second vertically-extending TFR side contacts. The TFR element includes a base portion extending laterally between the TFR side contacts, and first and second TFR element end flanges projecting vertically from opposing ends of the base portion. The first TFR element end flange is formed on a sidewall of the first TFR side contact, and the second TFR element end flange is formed on a sidewall of the second TFR side contact. A first TFR head contacts the first TFR side contact and a top of the first TFR element end flange, and a second TFR head contacts the second TFR side contact and a top of the second TFR element end flange, thus defining two parallel conductive paths between the TFR element and each TFR head.

公开(公告)号：US20230096226A1

公开(公告)日：2023-03-30

申请号：US18074617

申请日：2022-12-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L49/02 ,  H01L23/522

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.