公开(公告)号：US06961810B2

公开(公告)日：2005-11-01

申请号：US10743962

申请日：2003-12-22

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00 ,  G11C15/04 ,  G06F12/02

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract translation: CAM器件在一个时钟周期内执行：（1）从比较总线接收比较数据; （2）收到指示; （3）比较数据与第一组CAM单元进行比较; （4）生成CAM阵列中存储与比较数据匹配的数据的位置的匹配地址; （5）访问存储在CAM阵列中的CAM单元的第二组中的数据，其中第二组CAM单元可以存储与匹配位置相关联的数据; 和（6）输出到输出总线匹配地址，存储在第二组CAM单元中的数据和/或对应于匹配地址或第二组CAM单元的状态信息。

公开(公告)号：US06944709B2

公开(公告)日：2005-09-13

申请号：US09999798

申请日：2001-10-31

Applicant: Bindiganavale S. Nataraj ,  Nilesh A. Gharia ,  Rupesh R. Roy ,  Jose P. Pereira ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Hok F. Wong

Inventor： Bindiganavale S. Nataraj ,  Nilesh A. Gharia ,  Rupesh R. Roy ,  Jose P. Pereira ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Hok F. Wong

IPC: G11C15/00 ,  G11C15/04 ,  H03K3/356 ,  H03K23/56 ,  G06F13/00

CPC classification number: H03K3/356139 ,  G11C15/00 ,  G11C15/04 ,  H03K23/56

Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.

Abstract translation: 一种内容可寻址存储器（CAM）装置，包括多个CAM块和块控制电路。 多个CAM块各自包括用于存储数据字的CAM单元的阵列和优先级数存储电路的阵列以存储优先权号。 每个优先权数字指示相对于数据字中的其他数据字的相应一个数据字的优先级。 块控制电路具有用于接收类码的输入和用于向多个CAM块输出多个选择信号的电路。 每个选择信号选择性地禁用多个CAM块中的相应一个参与根据类代码的比较操作。

公开(公告)号：US06898099B1

公开(公告)日：2005-05-24

申请号：US10679073

申请日：2003-10-02

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.

Abstract translation: 内容可寻址存储器（CAM）架构。 对于一个实施例，CAM架构包括多个CAM单元行，每行被配置为在对应的匹配线上生成匹配结果，多个比较线，每个耦合到多行行中的每一行中的相应CAM单元 CAM单元，多个定时存储电路，每个具有耦合到对应匹配线的数据输入并具有耦合到使能信号线的使能输入的定时存储电路;定时发生器，被配置为在使能信号线上产生使能信号;以及 多个负载元件。

公开(公告)号：US06678786B2

公开(公告)日：2004-01-13

申请号：US10318251

申请日：2002-12-11

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G06F1206

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content address memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells. The status information may include a match flag, multiple match flag, full flag, skip bit, empty bit, or a device identification for the CAM device.

Abstract translation: 内容地址存储器（CAM）设备。 CAM设备是同步设备，其可以在一个时钟周期内执行所有以下操作：（1）从比较总线接收比较数据; （2）从指令总线接收指令，指示CAM设备将比较数据与CAM阵列中的第一组CAM单元进行比较; （3）比较数据与第一组CAM单元进行比较; （4）生成CAM阵列中存储与比较数据匹配的数据的位置的匹配地址; （5）访问存储在CAM阵列中的CAM单元的第二组中的数据，其中第二组CAM单元可以存储与匹配位置相关联的数据; 和（6）向输出总线输出匹配地址，存储在第二组CAM单元中的数据和/或与匹配地址或第二组CAM单元相对应的状态信息。 状态信息可以包括用于CAM设备的匹配标志，多重匹配标志，满标志，跳过位，空位或设备标识。

公开(公告)号：US06650575B1

公开(公告)日：2003-11-18

申请号：US10040714

申请日：2001-12-28

Applicant: Sandeep Khanna

Inventor： Sandeep Khanna

IPC: G11C700

CPC classification number: G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C15/00 ,  H03K5/1508 ,  H03K2005/00058

Abstract: An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.

Abstract translation: 一种具有耦合到内容可寻址存储器（CAM）阵列的输出寄存器的装置。 输出寄存器可以被配置为基于延迟的时钟信号输出数据。 可编程延迟电路可以被耦合以接收参考时钟信号并且使用一个或多个延迟元件产生延迟的时钟信号。

公开(公告)号：US06591331B1

公开(公告)日：2003-07-08

申请号：US09455726

申请日：1999-12-06

Applicant: Sandeep Khanna

Inventor： Sandeep Khanna

IPC: G06F1200

CPC classification number: G11C15/00

Abstract: A method and apparatus for determining the address of a highest priority matching entry in a segmented content addressable memory device. For one embodiment, a segmented CAM device is disclosed that includes m CAM array blocks each having n rows of CAM cells coupled to one of n corresponding match lines. The CAM array blocks have a predetermined priority based on their addresses such that the first CAM array block has the highest priority addresses and the mth CAM array block has the lowest priority addresses. Comparand data is provided for comparison with entries in each of the CAM array blocks. Each row of CAM cells in each block has a row enable logic circuit. A main priority encoder is coupled to the row enable logic circuits of the mth CAM array block. Each CAM array block also has an associated match flag circuit to determine a match flag signal for the block. A block priority encoder encodes the match flag signals into a block address of the highest priority matching location. The block address is provided to a decoder that decodes the block address. The decoded block address enables one of the groups of row enable logic circuits associated with the CAM array block having the highest priority matching location to provide its match results to the main priority encoder. The main priority encoder determines the subblock address of the matching entry in that CAM array block. The block address and the subblock address form the address of the highest priority matching entry or location in the entire CAM array.

Abstract translation: 一种用于确定分段内容可寻址存储设备中最高优先级匹配条目的地址的方法和装置。 对于一个实施例，公开了一种分段CAM设备，其包括m个CAM阵列块，每个CAM阵列块具有耦合到n个相应匹配线之一的n行CAM单元。 CAM阵列块基于它们的地址具有预定的优先权，使得第一CAM阵列块具有最高优先级地址，并且第m个CAM阵列块具有最低优先级地址。 提供比较数据以与每个CAM阵列块中的条目进行比较。 每个块中的每一行CAM单元具有行使能逻辑电路。 主要优先级编码器耦合到第m个CAM阵列块的行使能逻辑电路。 每个CAM阵列块还具有相关联的匹配标志电路，以确定块的匹配标志信号。 块优先编码器将匹配标志信号编码成最高优先级匹配位置的块地址。 块地址被提供给解码块地址的解码器。 解码块地址使得与具有最高优先级匹配位置的CAM阵列块相关联的行使能逻辑电路中的一个能够将其匹配结果提供给主优先级编码器。 主要优先级编码器确定该CAM阵列块中匹配条目的子块地址。 块地址和子块地址形成整个CAM阵列中最高优先级匹配条目或位置的地址。

公开(公告)号：US06275426B1

公开(公告)日：2001-08-14

申请号：US09420516

申请日：1999-10-18

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C700

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C29/785 ,  G11C29/816

Abstract: A method and apparatus for performing row redundancy in a CAM device. For one embodiment, the CAM device includes a main CAM array having a plurality of rows of CAM cells, main match line control circuitry coupled to the main CAM array, a spare row of CAM cells, and a spare match line control circuit coupled to the spare row of CAM cells. The main CAM array includes a plurality of main match lines each coupled to one of the plurality of rows of CAM cells, and a plurality of main word lines each coupled to one of the plurality of rows of CAM cells. For one embodiment, the main match line control circuitry comprises a plurality of latch circuits each having a data input coupled to one of the main word lines, an output coupled to one of the main match lines, and a clock input responsive to a reset signal and a repair signal. The repair signal indicates whether one of the plurality or rows in the first main CAM array is to be replaced by the spare row of CAM cells. The repair signal is also provided to the spare match line control circuit to enable the spare row of CAM cells when a CAM cell in the main CAM array is determined to be defective. During a reset operation, the latch circuits force a mismatch state on the main match line of a row in the main CAM array that has a defective CAM cell.

Abstract translation: 一种用于在CAM设备中执行行冗余的方法和装置。 对于一个实施例，CAM设备包括具有多个CAM单元行的主CAM阵列，耦合到主CAM阵列的主匹配线控制电路，CAM单元的备用行以及耦合到该CAM单元的备用匹配线控制电路 备用的CAM单元格。 主CAM阵列包括多个主匹配线，每条主要匹配线分别耦合到多个CAM单元的行之一，以及多个主字线，每条主字线都耦合到多个CAM单元之一。 对于一个实施例，主匹配线控制电路包括多个锁存电路，每个锁存电路具有耦合到主字线之一的数据输入，耦合到主匹配线之一的输出和响应于复位信号的时钟输入 和修复信号。 修复信号指示第一主CAM阵列中的多个或多个行中的一个是否由CAM单元的备用行替换。 修复信号也被提供给备用匹配线控制电路，以便当主CAM阵列中的CAM单元被确定为有缺陷时，能够使CAM单元的备用行。 在复位操作期间，锁存电路在具有缺陷的CAM单元的主CAM阵列中的一行的主匹配线上强制失配状态。

公开(公告)号：US06240485B1

公开(公告)日：2001-05-29

申请号：US09076336

申请日：1998-05-11

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G06F1200

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A method and apparatus for implementing a LEARN instruction in a depth cascaded content address memory (CAM) system. Each CAM device in the CAM system may include a CAM array, an input coupled to the CAM array and configured to receive comparand data to be compared with data stored in the CAM array, circuitry coupled to the CAM array and configured to write the comparand data into the CAM array if the comparand data does not match the data stored in the CAM array, and cascade logic coupled to the circuitry and configured to receive a plurality of match flag input signals, the cascade logic configured to disable the circuitry from writing the comparand data into the CAM array if the comparand data matches the data stored in the CAM array. Each CAM device may have a match flag input pin and output pin coupled to a match flag output pin and input pin, respectively, of the previous device and next device in the depth cascaded CAM system. Each CAM device may further include a cascade input pin and output pin coupled to a cascade output pin and input pin, respectively, of the previous device and next device in the depth cascaded CAM system.

Abstract translation: 一种用于在深度级联内容地址存储器（CAM）系统中实现LEARN指令的方法和装置。 CAM系统中的每个CAM设备可以包括CAM阵列，耦合到CAM阵列并被配置为接收与要与CAM阵列中存储的数据进行比较的比较数据的输入，耦合到CAM阵列的电路并被配置为写入比较数据 如果比较数据与存储在CAM阵列中的数据不匹配，则级联逻辑耦合到CAM阵列，并且被配置为接收多个匹配标志输入信号的级联逻辑，所述级联逻辑被配置为禁止电路写入比较 如果比较数据与存储在CAM阵列中的数据匹配，则数据进入CAM阵列。 每个CAM设备可以具有匹配标志输入引脚和输出引脚，其分别耦合到先前设备的匹配标志输出引脚和输入引脚以及深度级联CAM系统中的下一个器件。 每个CAM设备还可以包括级联输入引脚和输出引脚，其分别耦合到先前设备的级联输出引脚和输入引脚以及深度级联CAM系统中的下一个器件。

公开(公告)号：US06219748B1

公开(公告)日：2001-04-17

申请号：US09076337

申请日：1998-05-11

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C1500

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A content address memory (CAM) device that implements a “LEARN” instruction. In response to the LEARN instruction, the CAM device compares comparand data with data stored in a CAM array of the CAM device. If a match is not found, the comparand data is written into the CAM array. For one example, the comparand data is written to the next free address of the CAM array. The learn instruction may further cause the CAM device to output the next free address after the comparand data has been written into the CAM array. For one embodiment, the learn instruction may be implemented in a single clock cycle.

Abstract translation: 实现“LEARN”指令的内容地址存储器（CAM）设备。 响应于LEARN指令，CAM设备将比较数据与存储在CAM设备的CAM阵列中的数据进行比较。 如果未找到匹配项，则将比较数据写入CAM阵列。 例如，比较数据被写入CAM阵列的下一个空闲地址。 在比较数据被写入CAM阵列之后，学习指令还可以使CAM设备输出下一个空闲地址。 对于一个实施例，学习指令可以在单个时钟周期内实现。

公开(公告)号：US6137707A

公开(公告)日：2000-10-24

申请号：US276885

申请日：1999-03-26

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna ,  Bindiganavale S. Nataraj

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna ,  Bindiganavale S. Nataraj

IPC: G11C15/00 ,  G11C15/04 ,  G11C15/02

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A method and apparatus for simultaneously performing a plurality compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of CAM cells, a first comparand register for storing first comparand data, and a second comparand register for storing second comparand data. Each CAM cell receives the first comparand data over a first set of compare lines, and receives the second comparand data over a second set of compare lines. Each CAM cell has a memory cell and multiple compare circuits that can individually and simultaneously compare the first and second comparand data with data stored in the memory cell. The result of each comparison is reflected on a corresponding match line. The match lines are then selectively coupled to a priority encoder to determine a match address corresponding to each compare operation. For one embodiment, the CAM cells may be ternary CAM cells each having a mask cell.

Abstract translation: 一种用于在内容可寻址存储器（CAM）装置中同时执行多个比较操作的方法和装置。 对于一个实施例，CAM设备包括具有多个CAM单元的CAM阵列，用于存储第一比较数据的第一比较寄存器和用于存储第二比较数据的第二比较寄存器。 每个CAM单元通过第一组比较线接收第一比较数据，并通过第二组比较线接收第二比较数据。 每个CAM单元具有存储单元和多个比较电路，其可以单独并同时地将第一和第二比较数据与存储在存储单元中的数据进行比较。 每个比较的结果反映在相应的匹配线上。 然后将匹配线选择性地耦合到优先级编码器以确定与每个比较操作相对应的匹配地址。 对于一个实施例，CAM单元可以是每个具有掩模单元的三元CAM单元。