公开(公告)号：US20220238520A1

公开(公告)日：2022-07-28

申请号：US17469939

申请日：2021-09-09

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8238

Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device including a plurality of vertically stacked transistors. For example, the method can include providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors. The method can further include uncovering the second layers. The method can further include forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors.

公开(公告)号：US20220139786A1

公开(公告)日：2022-05-05

申请号：US17237628

申请日：2021-04-22

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include providing a substrate. The substrate can include a first type region and a second type region. The method can also include forming a multilayer stack on the substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming first and second openings through the multilayer stack to uncover the first and second type regions, respectively. The method can also include forming first and second vertical channel structures within the first and second openings, respectively. Each of the first and second vertical channel structures can have source, gate and drain regions being in contact with vertical sidewalls of the metal layers of the multilayer stack uncovered by a respective one of the first and second openings.

公开(公告)号：US20220102552A1

公开(公告)日：2022-03-31

申请号：US17315958

申请日：2021-05-10

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L29/78 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a floating body vertical field effect transistor with dielectric core and a method for fabricating the same. The floating body vertical field effect transistor can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures and can include a second semiconductor device formed on the same substrate adjacent to the first semiconductor device; a salicide layer or doped layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The floating body vertical field effect transistor may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break.

公开(公告)号：US20220102533A1

公开(公告)日：2022-03-31

申请号：US17316019

申请日：2021-05-10

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: Aspects of the present disclosure provide a 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures; a second semiconductor device formed on the same substrate adjacent to the first semiconductor device that includes sidewall structures of a second gate metal sandwiched by dielectric layers, a second epitaxially grown channel surrounded by the sidewall structures; a salicide layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The 3D semiconductor apparatus may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break.

公开(公告)号：US20220059413A1

公开(公告)日：2022-02-24

申请号：US17108525

申请日：2020-12-01

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques herein include methods for fabricating complete field effect transistors having an upright or vertical orientation. The methods can utilize epitaxial growth to provide fine control over material deposition and thickness of said material layers. The methods can provide separate control of channel doping in either NMOS and/or PMOS transistors. All of a source, channel, and drain can be epitaxially grown in an opening into a dielectric layer stack, with said doping executed during said epitaxial growth.

公开(公告)号：US20210391207A1

公开(公告)日：2021-12-16

申请号：US17094947

申请日：2020-11-11

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A method of microfabrication is provided. An initial stack of layers is formed over a semiconductor layer. The initial stack of layers can include a plurality of substacks separated from each other by one or more transition layers. One or more of the substacks include a sacrificial gate layer sandwiched between two first dielectric layers. Openings can be formed in the initial stack of layers so that the semiconductor layer is uncovered. The openings can be filled with vertical channel structures, where each vertical channel structure extends through a respective substack. The initial stack can be divided into separate stacks that include the vertical channel structures surrounded by the substacks and the transition layers. The one or more transition layers can be removed from the separate stacks to uncover transition points between neighboring vertical channel structures. Isolation structures can be formed at the transition points.

公开(公告)号：US20210366904A1

公开(公告)日：2021-11-25

申请号：US17113736

申请日：2020-12-07

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L27/06 ,  H01L21/8238

Abstract: Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device

公开(公告)号：US20210366787A1

公开(公告)日：2021-11-25

申请号：US17115122

申请日：2020-12-08

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device can include a pad layer including at least one pad structure having a core area surrounded by a peripheral area, and a transistor over the core area. The transistor includes a channel structure extending vertically and a gate structure all around a sidewall portion of the channel structure. The channel structure has a source region and a drain region on opposing ends of a vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. The semiconductor device can further include a first vertical interconnect structure that contacts a top surface of the channel structure, a second vertical interconnect structure that contacts the peripheral area and is configured to be coupled to a bottom surface of the channel structure via the pad structure, and a third vertical interconnect structure that is positioned away from the channel structure and contacts the gate structure.

公开(公告)号：US20210175209A1

公开(公告)日：2021-06-10

申请号：US16841648

申请日：2020-04-06

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/8234 ,  H01L25/00 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088

Abstract: A semiconductor device includes an NMOS device formed on a first substrate bonded with a second substrate having a PMOS device formed thereon, with the bonding achieved by contacting a first wiring layer formed on the NMOS device with a second wiring layer formed on the PMOS device.