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    WAFER SUPPORT FOR MEASURING WAFER GEOMETRY
    1.
    发明申请
    WAFER SUPPORT FOR MEASURING WAFER GEOMETRY 有权

    公开(公告)号：US20250167024A1

    公开(公告)日：2025-05-22

    申请号：US18511557

    申请日：2023-11-16

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L21/67 ,  G01B21/20 ,  H01L21/66

    Abstract: A wafer measurement stage for supporting a semiconductor wafer for surface geometry measurements. The wafer measurement stage includes a support body having a planar surface configured to face a wafer which is supported by the wafer measurement stage, and a wafer contact structure provided on the planar surface. The wafer contact structure is configured to contact a portion of a wafer such that the wafer is supported in an elevated position relative to the planar surface and to control gravity effects at non-contact portions of the wafer.

    DEVICE AND METHOD OF FORMING 3D U-SHAPED NANOSHEET CFET
    2.
    发明公开
    DEVICE AND METHOD OF FORMING 3D U-SHAPED NANOSHEET CFET 审中-公开

    公开(公告)号：US20240249978A1

    公开(公告)日：2024-07-25

    申请号：US18159462

    申请日：2023-01-25

    Applicant: Tokyo Electron Limited

    Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

    IPC: H01L21/822 ,  H01L27/088

    CPC classification number: H01L21/8221 ,  H01L27/088

    Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

    3D MEMORY WITH CELL STACKING USING AN IN-SITU CAPACITOR STACK
    4.
    发明公开
    3D MEMORY WITH CELL STACKING USING AN IN-SITU CAPACITOR STACK 审中-公开

    公开(公告)号：US20230301058A1

    公开(公告)日：2023-09-21

    申请号：US17946715

    申请日：2022-09-16

    Applicant: Tokyo Electron Limited

    Inventor： Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

    Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer on the first metal layer, and a second metal layer on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction. The first metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure on the channel structure. The second metal layer extends in the horizontal direction beyond the first end of the first metal layer to form a drain region and a source region of the transistor. A common ground structure is configured to electrically connect to a plurality of first metal layers on respective second ends.

    3D NANO SHEET WITH HIGH DENSITY 3D METAL ROUTING
    6.
    发明公开
    3D NANO SHEET WITH HIGH DENSITY 3D METAL ROUTING 审中-公开

    公开(公告)号：US20230178436A1

    公开(公告)日：2023-06-08

    申请号：US17873745

    申请日：2022-07-26

    Applicant: Tokyo Electron Limited

    Inventor： Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L21/8234 ,  H01L21/822 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

    CPC classification number: H01L21/823475 ,  H01L21/8221 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0673

    Abstract: A method of microfabrication includes forming a stack of source/drain (S/D) contact structures over a substrate. The S/D contact structures are vertically separated. Gate contact structures are formed over the substrate and vertically separated. A first opening is formed so that middle portions of the S/D contact structures are removed while end portions of the S/D contact structures are positioned on opposing sides of the first opening. A layer stack is formed within the first opening, and includes channel structures stacked over the substrate, vertically separated and connected to respective end portions of the S/D contact structures. Second openings are formed, each uncovering a respective side surface of the layer stack and a respective side surface of at least one gate contact structure. Gate structures are formed in the second openings so that each gate structure is connected to a respective gate contact structure and a respective channel structure.

    3D DEVICES WITH 3D DIFFUSION BREAKS AND METHOD OF FORMING THE SAME
    8.
    发明申请
    3D DEVICES WITH 3D DIFFUSION BREAKS AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220254925A1

    公开(公告)日：2022-08-11

    申请号：US17480361

    申请日：2021-09-21

    Applicant: Tokyo Electron Limited

    Inventor： Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

    Abstract: A semiconductor device is provided. The semiconductor device includes a first layer including a first semiconductor material. Shell structures are positioned above and electrically isolated from the first layer. The shell structures include at least one type of semiconductor material. Each shell structure is configured to include a channel region oriented in a vertical direction perpendicular to the first layer and have a current flow path in the vertical direction. The semiconductor device also includes an inner structure positioned on an inner sidewall of a respective channel region of each shell structure. The semiconductor device further includes gate structures including an outer gate structure positioned on an outer sidewall of a respective channel region of each shell structure.

    METHOD OF MAKING VERTICAL SEMICONDUCTOR NANOSHEETS WITH DIFFUSION BREAKS
    9.
    发明申请
    METHOD OF MAKING VERTICAL SEMICONDUCTOR NANOSHEETS WITH DIFFUSION BREAKS 有权

    公开(公告)号：US20220254689A1

    公开(公告)日：2022-08-11

    申请号：US17480318

    申请日：2021-09-21

    Applicant: Tokyo Electron Limited

    Inventor： Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L21/8234 ,  H01L21/8238

    Abstract: A method of microfabrication includes providing a substrate having a first layer including a first semiconductor material. A second layer of a second semiconductor material is formed over the first layer. The second layer is directionally etched using a mask to form independent core structures of the second semiconductor material on the first semiconductor material. A third layer of a first dielectric material is formed on an exposed surface of the first layer to cover a lower portion of a respective sidewall of each core structure. A shell structure is formed on an upper portion of a respective sidewall of each core structure to form shell structures including at least one semiconductor material. The core structures are removed such that each shell structure forms a vertical semiconductor structure extending vertically from the first layer and electrically isolated from the first semiconductor material by the first dielectric material.

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