公开(公告)号：US20170317090A1

公开(公告)日：2017-11-02

申请号：US15635165

申请日：2017-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US09799650B2

公开(公告)日：2017-10-24

申请号：US15043614

申请日：2016-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207

Abstract: A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended along a first direction, and the Vss lines are arranged along a second direction. The first direction and the second direction are perpendicular to each other. The Vss lines are arranged at respective two sides of the first signal line.

公开(公告)号：US20170200717A1

公开(公告)日：2017-07-13

申请号：US15043614

申请日：2016-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207

Abstract: A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended along a first direction, and the Vss lines are arranged along a second direction. The first direction and the second direction are perpendicular to each other. The Vss lines are arranged at respective two sides of the first signal line.