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公开(公告)号：US20240363749A1
公开(公告)日：2024-10-31
申请号：US18766753
申请日：2024-07-09
发明人： Yu-Lien Huang , Peng Wang
IPC分类号： H01L29/78 , H01L21/02 , H01L21/3065 , H01L21/311 , H01L21/321 , H01L21/768 , H01L29/66
CPC分类号： H01L29/7835 , H01L21/02274 , H01L21/0228 , H01L21/3065 , H01L21/311 , H01L21/31116 , H01L21/3212 , H01L21/76829 , H01L29/66659 , H01L29/6681
摘要： The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.
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公开(公告)号：US20240363431A1
公开(公告)日：2024-10-31
申请号：US18766881
申请日：2024-07-09
IPC分类号： H01L21/8234 , H01L21/308 , H01L29/08 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/3086 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/0847 , H01L29/66545 , H01L29/6659 , H01L29/6681 , H01L29/7834 , H01L29/7851
摘要： A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.
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公开(公告)号：US12125707B2
公开(公告)日：2024-10-22
申请号：US17814607
申请日：2022-07-25
发明人： Yu-Li Lin , Chih-Teng Liao , Jui Fu Hsieh , Chih Hsuan Cheng , Tzu-Chan Weng
IPC分类号： H01L21/3065 , H01J37/32 , H01L21/8234 , H01L29/66 , H01L29/78
CPC分类号： H01L21/3065 , H01J37/32174 , H01L21/823431 , H01L29/6681 , H01L29/785
摘要： A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.
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公开(公告)号：US20240347390A1
公开(公告)日：2024-10-17
申请号：US18753406
申请日：2024-06-25
IPC分类号： H01L21/8234 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/088 , H01L27/092 , H01L29/66
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/823431 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L29/6681
摘要： In an embodiment, a device includes a first active region over a substrate, a portion of the first active region having a first surface, the first surface defining a channel and being a first distance from the substrate. A dummy structure is adjacent to the first active region and has a sidewall extending from the substrate to a second surface facing way from the substrate, the second surface being a second distance, less than the first distance, from the substrate. An isolation region extends from a sidewall of a lower portion of the first active region over the second surface of the dummy semiconductor structure.
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5.发明授权公开(公告)号：US12119351B2
公开(公告)日：2024-10-15
申请号：US17508704
申请日：2021-10-22
发明人： Dong-Il Bae , Kang-Ill Seo
IPC分类号： H01L27/092 , H01L21/3105 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H01L27/0924 , H01L21/31053 , H01L21/823431 , H01L27/0886 , H01L29/0673 , H01L29/0847 , H01L29/161 , H01L29/42364 , H01L29/42392 , H01L29/66439 , H01L29/6681 , H01L29/775 , H01L29/785 , H01L29/7851 , H01L29/78696
摘要： A method of manufacturing a semiconductor device includes forming a fin structure on a substrate. A sacrificial layer pattern is formed on the fin structure. An active layer pattern is formed on the sacrificial layer pattern. A dummy gate pattern is formed on the active layer pattern. A spacer is formed on the dummy gate pattern. A source/drain structure is formed on the active layer pattern using an epitaxial growth process. An interlayer dielectric layer is formed on the dummy gate pattern and the active layer pattern. The interlayer dielectric layer is planarized to expose the dummy gate pattern. The dummy gate pattern is removed to expose the active layer pattern and the sacrificial layer pattern. The exposed sacrificial layer pattern is removed to form a through-hole between the exposed active layer pattern and the fin structure, the second portion of the sacrificial layer pattern is not removed.
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公开(公告)号：US12094975B2
公开(公告)日：2024-09-17
申请号：US18360457
申请日：2023-07-27
发明人： Sangmoon Lee , Kyungin Choi , Seunghun Lee
IPC分类号： H01L31/113 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/78 , H01L31/119
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/41791 , H01L29/6681
摘要： An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.
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公开(公告)号：US20240304620A1
公开(公告)日：2024-09-12
申请号：US18670223
申请日：2024-05-21
发明人： Yi-Chun Chen , Jih-Jse Lin , Ryan Chia-Jen Chen
IPC分类号： H01L27/088 , H01L21/306 , H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/30608 , H01L21/823431 , H01L29/0649 , H01L29/6681 , H01L29/7851
摘要： A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.
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公开(公告)号：US12087842B2
公开(公告)日：2024-09-10
申请号：US18336788
申请日：2023-06-16
发明人： Bone-Fong Wu , Chih-Hao Yu , Chia-Pin Lin
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78 , H01L21/02
CPC分类号： H01L29/66553 , H01L29/0653 , H01L29/42392 , H01L29/6653 , H01L29/6656 , H01L29/6681 , H01L29/7853 , H01L21/0214 , H01L21/0228
摘要： A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.
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公开(公告)号：US20240290886A1
公开(公告)日：2024-08-29
申请号：US18654766
申请日：2024-05-03
IPC分类号： H01L29/78 , H01L27/088 , H01L29/06 , H01L29/16 , H01L29/417 , H01L29/66
CPC分类号： H01L29/785 , H01L27/0886 , H01L29/0665 , H01L29/16 , H01L29/41791 , H01L29/66545 , H01L29/6681 , H01L29/66818
摘要： A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.
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公开(公告)号：US12068318B2
公开(公告)日：2024-08-20
申请号：US18446185
申请日：2023-08-08
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L29/6656 , H01L29/6681 , H01L29/7851
摘要： Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.
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