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公开(公告)号:US20190245065A1
公开(公告)日:2019-08-08
申请号:US16390172
申请日:2019-04-22
发明人: I-Sheng CHEN , Cheng-Hsien WU , Chih-Chieh YEH
IPC分类号: H01L29/66 , H01L27/088 , H01L29/06 , H01L29/739 , H01L29/10
CPC分类号: H01L29/66795 , H01L21/28518 , H01L27/088 , H01L29/0673 , H01L29/1033 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6681 , H01L29/7391 , H01L29/775
摘要: A device includes a substrate, a first doping portion, a second doping portion, a channel, a semiconductor film, a high-k layer, and a gate. The first doping portion and the second doping portion are over the substrate. The channel is over the substrate and between the first doping portion and the second doping portion. The semiconductor film is around the channel. The high-k layer is around the semiconductor film. The gate is over the high-k layer.
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公开(公告)号:US10366926B1
公开(公告)日:2019-07-30
申请号:US16390246
申请日:2019-04-22
发明人: Che-Cheng Chang , Chih-Han Lin
IPC分类号: H01L21/28 , H01L21/3105 , H01L21/311 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L21/321
CPC分类号: H01L21/823431 , H01L21/28079 , H01L21/28088 , H01L21/31051 , H01L21/31111 , H01L21/32115 , H01L27/0886 , H01L29/0649 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
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3.
公开(公告)号:US20190229195A1
公开(公告)日:2019-07-25
申请号:US16370025
申请日:2019-03-29
IPC分类号: H01L29/417 , H01L29/78 , H01L29/66 , H01L21/02 , H01L29/423 , H01L29/165 , H01L21/283
CPC分类号: H01L29/41783 , H01L21/02532 , H01L21/02636 , H01L21/283 , H01L29/165 , H01L29/42364 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/7848 , H01L29/785
摘要: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.
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公开(公告)号:US20190221641A1
公开(公告)日:2019-07-18
申请号:US16327034
申请日:2016-09-30
申请人: INTEL CORPORATION
IPC分类号: H01L29/06 , H01L29/165 , H01L29/78 , H01L29/10 , H01L29/08 , H01L29/66 , H01L21/8234 , H01L21/02
CPC分类号: H01L29/0673 , B82Y10/00 , H01L21/02527 , H01L21/02532 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L29/06 , H01L29/0847 , H01L29/1033 , H01L29/165 , H01L29/66 , H01L29/66439 , H01L29/66545 , H01L29/6681 , H01L29/775 , H01L29/785
摘要: Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires. The carbon concentration of the sacrificial and/or non-sacrificial layers can be adjusted to facilitate etch process to liberate nanowires in the channel region.
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公开(公告)号:US20190221638A1
公开(公告)日:2019-07-18
申请号:US15872610
申请日:2018-01-16
IPC分类号: H01L29/06 , H01L29/78 , H01L21/761 , H01L29/66
CPC分类号: H01L29/0646 , H01L21/761 , H01L29/0673 , H01L29/6653 , H01L29/66553 , H01L29/6681 , H01L29/7853
摘要: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.
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6.
公开(公告)号:US20190214311A1
公开(公告)日:2019-07-11
申请号:US16241677
申请日:2019-01-07
发明人: Indira Seshadri , Ekmini Anuja De Silva , Jing Guo , Romain J. Lallement , Ruqiang Bao , Zhenxing Bi , Sivananda Kanakasabapathy
IPC分类号: H01L21/8238 , H01L21/28 , H01L27/092 , H01L21/308
CPC分类号: H01L21/823842 , H01L21/28185 , H01L21/3081 , H01L21/8221 , H01L21/823821 , H01L27/0688 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/6653 , H01L29/66553 , H01L29/6681 , H01L29/7853
摘要: A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
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公开(公告)号:US20190206999A1
公开(公告)日:2019-07-04
申请号:US15861167
申请日:2018-01-03
发明人: Peng Xu , Kangguo Cheng , Juntao Li , Heng Wu
IPC分类号: H01L29/10 , H01L29/66 , H01L21/02 , H01L21/3065 , H01L21/308 , H01L21/762 , H01L29/78 , H01L29/165 , H01L29/06
CPC分类号: H01L29/1054 , H01L21/02532 , H01L21/3065 , H01L21/308 , H01L21/76224 , H01L29/0653 , H01L29/165 , H01L29/66545 , H01L29/6681 , H01L29/7851
摘要: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.
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公开(公告)号:US20190131184A1
公开(公告)日:2019-05-02
申请号:US16217738
申请日:2018-12-12
IPC分类号: H01L21/8238 , H01L27/092
CPC分类号: H01L21/823821 , H01L21/30604 , H01L21/3065 , H01L21/31116 , H01L21/823814 , H01L21/823842 , H01L21/82385 , H01L21/823871 , H01L27/0924 , H01L29/0673 , H01L29/401 , H01L29/6653 , H01L29/66553 , H01L29/6681 , H01L29/7853
摘要: A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.
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公开(公告)号:US20190097055A1
公开(公告)日:2019-03-28
申请号:US16081572
申请日:2016-04-01
申请人: INTEL CORPORATION
发明人: GILBERT DEWEY , TAHIR GHANI , WILLY RACHMADY , JACK T. KAVALIEROS , MATTHEW V. METZ , ANAND S. MURTHY , CHANDRA S. MOHAPATRA
IPC分类号: H01L29/78 , H01L29/423 , H01L29/66 , H01L29/10 , H01L29/08 , H01L21/8238
CPC分类号: H01L29/7853 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823878 , H01L29/0847 , H01L29/1054 , H01L29/4236 , H01L29/66545 , H01L29/6656 , H01L29/6681 , H01L29/66818
摘要: Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.
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公开(公告)号:US20190096765A1
公开(公告)日:2019-03-28
申请号:US15718740
申请日:2017-09-28
发明人: Kuo-Cheng CHING , Chih-Hao WANG , Kuan-Lun CHENG
IPC分类号: H01L21/8234 , H01L23/535 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/66
CPC分类号: H01L21/823418 , H01L21/823412 , H01L21/823431 , H01L21/823475 , H01L21/823481 , H01L23/535 , H01L27/0886 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/6681
摘要: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.
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