公开(公告)号：US07925011B2

公开(公告)日：2011-04-12

申请号：US11610919

申请日：2006-12-14

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Kaan Yuksel ,  Gunnar Gaubatz ,  Wajdi Feghali ,  Gilbert M. Wolrich

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Kaan Yuksel ,  Gunnar Gaubatz ,  Wajdi Feghali ,  Gilbert M. Wolrich

IPC分类号： H04L9/00

CPC分类号： G06F7/723 ,  H04L9/302

摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种用于执行模幂运算的方法。 该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q） ）。 该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数 第二余数（xq）升至第二素数（q）的第二私钥号（d2）。 该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。 该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。 该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20140177823A1

公开(公告)日：2014-06-26

申请号：US13727141

申请日：2012-12-26

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford

IPC分类号： H04L9/28

CPC分类号： H04L9/0637 ,  G06F9/00 ,  G06F9/30032 ,  G06F21/00 ,  H04L2209/12

摘要： Methods and apparatus are disclosed to reduce processor demands during encryption. A disclosed example method includes detecting a request for the processor to execute an encryption cipher determining whether the encryption cipher is associated with a byte reflection operation, preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition, and incrementing the buffer via a shift operation before executing the encryption cipher.

摘要翻译： 公开了减少加密期间处理器需求的方法和装置。 所公开的示例方法包括：检测处理器执行确定加密密码是否与字节反射操作相关联的加密密码的请求，当与加密密码相关联的缓冲器不会导致携带条件时，防止字节反射操作;以及 在执行加密密码之前通过移位操作递增缓冲区。

公开(公告)号：US20080144810A1

公开(公告)日：2008-06-19

申请号：US11610886

申请日：2006-12-14

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

IPC分类号： H04L9/30

CPC分类号： G06F7/723

摘要： The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种用于执行模幂运算的系统和方法。 该方法可以包括将第一多项式划分成多个段，并通过将第一多项式的多个段乘以第二多项式来生成第一乘积。 该方法还可以包括通过用因式分解基座移位累加器的内容来产生第二乘积。 该方法还可以包括添加第一产物和第二产物以产生第一中间结果并减少第一中间结果以产生第二中间结果。 该方法还可以包括至少部分地基于第二中间结果生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US07961877B2

公开(公告)日：2011-06-14

申请号：US11610886

申请日：2006-12-14

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

IPC分类号： H04L9/30 ,  H04L9/28 ,  H04L9/00 ,  G06G7/16

CPC分类号： G06F7/723

摘要： The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种用于执行模幂运算的系统和方法。 该方法可以包括将第一多项式划分成多个段，并通过将第一多项式的多个段乘以第二多项式来生成第一乘积。 该方法还可以包括通过用因式分解基座移位累加器的内容来产生第二乘积。 该方法还可以包括添加第一产物和第二产物以产生第一中间结果并减少第一中间结果以产生第二中间结果。 该方法还可以包括至少部分地基于第二中间结果生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20100153829A1

公开(公告)日：2010-06-17

申请号：US12336029

申请日：2008-12-16

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

IPC分类号： H03M13/09 ,  G06F7/72 ,  G06F11/10

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

摘要翻译： 在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值 另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

公开(公告)号：US20110106872A1

公开(公告)日：2011-05-05

申请号：US12157074

申请日：2008-06-06

申请人： William Hasenplaugh ,  Gilbert Wolrich ,  Vinodh Gopal ,  Gunnar Gaubatz ,  Erdinc Ozturk ,  Wajdi Feghali

发明人： William Hasenplaugh ,  Gilbert Wolrich ,  Vinodh Gopal ,  Gunnar Gaubatz ,  Erdinc Ozturk ,  Wajdi Feghali

IPC分类号： G06F7/487

CPC分类号： G06F7/5324 ,  G06F7/72

摘要： An area efficient multiplier having high performance at modest clock speeds is presented. The performance of the multiplier is based on optimal choice of a number of levels of Karatsuba decomposition. The multiplier may be used to perform efficient modular reduction of large numbers greater than the size of the multiplier.

摘要翻译： 提出了一种在适度的时钟速度下具有高性能的区域有效乘法器。 乘数的表现是基于对Karatsuba分解的多个水平的最佳选择。 乘法器可用于执行大于乘数大小的大数量的有效的模块化减少。

公开(公告)号：US20090158132A1

公开(公告)日：2009-06-18

申请号：US12291621

申请日：2008-11-12

申请人： Vinodh Gopal ,  Gilbert Wolrich ,  Wajdi Feghali ,  Erdinc Ozturk ,  Shay Gueron

发明人： Vinodh Gopal ,  Gilbert Wolrich ,  Wajdi Feghali ,  Erdinc Ozturk ,  Shay Gueron

IPC分类号： H03M13/09 ,  G06F7/72 ,  G06F17/14 ,  G06F11/10 ,  G06F5/01

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.

摘要翻译： 在一个方面，用于确定相对于包括一系列段的消息的多项式的模块余数的电路。 在另一方面，访问具有第一末端格式的第一号码的至少一部分的电路基于具有与第一末端格式相反的端格式的第三号码的位反射和位移来确定第二号码，以及 执行第一数字和第一数字的至少一部分的多项式相乘。

公开(公告)号：US09292283B2

公开(公告)日：2016-03-22

申请号：US13707105

申请日：2012-12-06

申请人： Erdinc Ozturk ,  Vinodh Gopal ,  James Guilford

发明人： Erdinc Ozturk ,  Vinodh Gopal ,  James Guilford

IPC分类号： G06F7/523 ,  G06F9/30 ,  G06F7/52

CPC分类号： G06F9/3001 ,  G06F7/52 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30036 ,  G06F2207/5523

摘要： Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all sub-elements within their respective columns, the added sub-elements collectively identified as T2, and (v) yielding a final 512-bit squared result of the 512-bit value by adding the value of T2 twice with the value of T1 once. Other related embodiments are disclosed.

摘要翻译： 公开了用于在诸如IA（Intel Architecture）处理器之类的集成电路内实现快速大整数运算的方法，系统和装置，其中这种装置包括接收512位的平方值，512位值具有 八个子元素，每个64位，并通过以下方式执行512位平方算法：（i）将八个子元素中的每一个本身相乘以产生八个子元素中的每一个的平方，八个子元素 - 集体标识为T1的元件，（ii）将八个子元素中的每一个乘以八个子元素中的其余七个子元素以产生其中具有七个对角线的不对称中间结果，其中七个对角线中的每一个为 （iii）将其中具有七个对角线的非对称中间结果重新组合成具有四个对角线的对称中间结果，每个对角线的长度为64位的7×1个子元素跨越多个 列，（iv）将其所有列中的所有子元素加入集体标识为T2的所添加的子元素，以及（v）通过将T2值增加两次来产生512位值的最终512位平方结果 其T1值一次。 公开了其他相关实施例。

公开(公告)号：US08042025B2

公开(公告)日：2011-10-18

申请号：US12291621

申请日：2008-11-12

申请人： Vinodh Gopal ,  Gilbert Wolrich ,  Wajdi Feghali ,  Erdinc Ozturk ,  Shay Gueron

发明人： Vinodh Gopal ,  Gilbert Wolrich ,  Wajdi Feghali ,  Erdinc Ozturk ,  Shay Gueron

IPC分类号： H03M13/03

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.

摘要翻译： 在一个方面，用于确定相对于包括一系列段的消息的多项式的模块余数的电路。 在另一方面，访问具有第一末端格式的第一号码的至少一部分的电路基于具有与第一末端格式相反的端格式的第三号码的位反射和位移来确定第二号码，以及 执行第一数字和第一数字的至少一部分的多项式相乘。

公开(公告)号：US08312363B2

公开(公告)日：2012-11-13

申请号：US12336029

申请日：2008-12-16

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

IPC分类号： G06F11/00

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

摘要翻译： 在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值 另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。