Carry/Borrow Handling
    1.
    发明申请
    Carry/Borrow Handling 审中-公开
    携带/借款处理

    公开(公告)号:US20080148011A1

    公开(公告)日:2008-06-19

    申请号:US11610897

    申请日:2006-12-14

    IPC分类号: G06F9/30

    CPC分类号: G06F9/3001

    摘要: The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译: 本公开提供了用于执行进位/借用处理的系统和方法。 根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果,并将第一进位或借位以及第一指针地址存储在临时寄存器中。 该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果,并调用被配置为执行进位和借位处理的子程序。 该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。 当然,在不脱离本实施例的情况下,可以进行许多替代,变化和修改。

    Method for simultaneous modular exponentiations
    2.
    发明授权
    Method for simultaneous modular exponentiations 有权
    同时采用模幂分析的方法

    公开(公告)号:US07925011B2

    公开(公告)日:2011-04-12

    申请号:US11610919

    申请日:2006-12-14

    IPC分类号: H04L9/00

    CPC分类号: G06F7/723 H04L9/302

    摘要: The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译: 本公开提供了一种用于执行模幂运算的方法。 该方法可以包括基于第一素数(p)模数的加密消息(X)生成第一余数(xp),并且基于加密消息(X)生成第二余数(xq),第二素数(q) )。 该方法还可以包括:基于第一余数(xp)产生第三余数(v1),所述第一余数(xp)基于所述第一余数(xp)生成第一素数(p)的第一私钥数(d1)并同时生成第四余数 第二余数(xq)升至第二素数(q)的第二私钥号(d2)。 该方法还可以包括从第三余数(v1)中减去第四余数(v2)以产生结果(v1-v2)并将结果(v1-v2)乘以常数(c)以产生第二结果。 该方法可以另外包括通过将第二结果以第一素数(p)取模并将第六余数(h)乘以第二素数(q)产生第三结果来产生第六余数(h)。 该方法还可以包括添加第三结果和第四余数(v2)以产生最终结果(Y),并且至少部分地基于最终结果(Y)生成公钥。 当然,在不脱离本实施例的情况下,可以进行许多替代,变化和修改。

    Method for Simultaneous Modular Exponentiations
    3.
    发明申请
    Method for Simultaneous Modular Exponentiations 有权
    同时模块化指标的方法

    公开(公告)号:US20080144811A1

    公开(公告)日:2008-06-19

    申请号:US11610919

    申请日:2006-12-14

    IPC分类号: H04L9/30

    CPC分类号: G06F7/723 H04L9/302

    摘要: The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译: 本公开提供了一种用于执行模幂运算的方法。 该方法可以包括基于第一素数(p)模数的加密消息(X)生成第一余数(xp),并且基于加密消息(X)生成第二余数(xq),第二素数(q) )。 该方法还可以包括:基于第一余数(xp)产生第三余数(v1),所述第一余数(xp)基于所述第一余数(xp)生成第一素数(p)的第一私钥数(d1)并同时生成第四余数 第二余数(xq)升至第二素数(q)的第二私钥号(d2)。 该方法还可以包括从第三余数(v1)中减去第四余数(v2)以产生结果(v1-v2)并将结果(v1-v2)乘以常数(c)以产生第二结果。 该方法可以另外包括通过将第二结果以第一素数(p)取模并将第六余数(h)乘以第二素数(q)产生第三结果来产生第六余数(h)。 该方法还可以包括添加第三结果和第四余数(v2)以产生最终结果(Y),并且至少部分地基于最终结果(Y)生成公钥。 当然,在不脱离本实施例的情况下,可以进行许多替代,变化和修改。

    Factoring Based Modular Exponentiation
    5.
    发明申请
    Factoring Based Modular Exponentiation 有权
    基于分数的模块化指数

    公开(公告)号:US20080144810A1

    公开(公告)日:2008-06-19

    申请号:US11610886

    申请日:2006-12-14

    IPC分类号: H04L9/30

    CPC分类号: G06F7/723

    摘要: The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译: 本公开提供了一种用于执行模幂运算的系统和方法。 该方法可以包括将第一多项式划分成多个段,并通过将第一多项式的多个段乘以第二多项式来生成第一乘积。 该方法还可以包括通过用因式分解基座移位累加器的内容来产生第二乘积。 该方法还可以包括添加第一产物和第二产物以产生第一中间结果并减少第一中间结果以产生第二中间结果。 该方法还可以包括至少部分地基于第二中间结果生成公钥。 当然,在不脱离本实施例的情况下,可以进行许多替代,变化和修改。

    Factoring based modular exponentiation
    6.
    发明授权
    Factoring based modular exponentiation 有权
    基于分数的模幂运算

    公开(公告)号:US07961877B2

    公开(公告)日:2011-06-14

    申请号:US11610886

    申请日:2006-12-14

    CPC分类号: G06F7/723

    摘要: The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译: 本公开提供了一种用于执行模幂运算的系统和方法。 该方法可以包括将第一多项式划分成多个段,并通过将第一多项式的多个段乘以第二多项式来生成第一乘积。 该方法还可以包括通过用因式分解基座移位累加器的内容来产生第二乘积。 该方法还可以包括添加第一产物和第二产物以产生第一中间结果并减少第一中间结果以产生第二中间结果。 该方法还可以包括至少部分地基于第二中间结果生成公钥。 当然,在不脱离本实施例的情况下,可以进行许多替代,变化和修改。

    RESIDUE GENERATION
    7.
    发明申请
    RESIDUE GENERATION 失效
    残留生成

    公开(公告)号:US20100153829A1

    公开(公告)日:2010-06-17

    申请号:US12336029

    申请日:2008-12-16

    IPC分类号: H03M13/09 G06F7/72 G06F11/10

    CPC分类号: G06F7/724 H03M13/091

    摘要: In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

    摘要翻译: 在一个实施例中,提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代,包括(a)将第一值与数据流的至少一部分相乘,以及(b)通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作,其包括(c)至少部分地基于所述减少,通过与另一个流的至少一部分乘以第二值来产生另一结果,(d)通过至少加入来产生第三值 另一个流的另一部分到另一个结果,以及(e)至少部分地基于第三个值执行巴雷特还原来产生残留物。

    Method and apparatus for efficient programmable cyclic redundancy check (CRC)
    9.
    发明授权
    Method and apparatus for efficient programmable cyclic redundancy check (CRC) 有权
    用于高效可编程循环冗余校验(CRC)的方法和装置

    公开(公告)号:US09052985B2

    公开(公告)日:2015-06-09

    申请号:US11963147

    申请日:2007-12-21

    IPC分类号: G06F7/72 H03M13/09

    CPC分类号: G06F7/724 G06F7/72 H03M13/09

    摘要: A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.

    摘要翻译: 一种在循环冗余校验(CRC)电路中优化多个还原级中的每一个以产生数据块的残差的方法和装置减少了用于执行减少的区域,同时通过多个阶段保持相同的延迟 还原逻辑。 在CRC减少电路中,Karatsuba算法,经典乘法和串行划分的混合混合结果导致平均面积减少了约20%,而关键路径延迟没有减少。