公开(公告)号：US11632088B2

公开(公告)日：2023-04-18

申请号：US17102455

申请日：2020-11-24

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Yang-Jing Huang ,  Deng-Yao Shih ,  Ya-Mien Hsu

IPC: H03F3/217 ,  H03F3/45 ,  H03K5/08 ,  H02M3/156

Abstract: A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

公开(公告)号：US20230116769A1

公开(公告)日：2023-04-13

申请号：US17499870

申请日：2021-10-13

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Po-Hsun Wu ,  Jen-Shou Hsu

IPC: G11C7/22

Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

公开(公告)号：US20220400341A1

公开(公告)日：2022-12-15

申请号：US17344907

申请日：2021-06-10

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Hsin-Yuan Chiu ,  Tsung-Fu Lin

IPC: H04R3/04 ,  H03G5/16 ,  H03G5/02 ,  H03G5/00

Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

公开(公告)号：US11368130B1

公开(公告)日：2022-06-21

申请号：US17179375

申请日：2021-02-18

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Hsin-Yuan Chiu ,  Hsiang-Yu Yang

IPC: H03F3/217 ,  H03F1/52 ,  H03F3/38

Abstract: A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.

公开(公告)号：US11342030B1

公开(公告)日：2022-05-24

申请号：US17145415

申请日：2021-01-11

Applicant: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.

Inventor： Ming-Xun Wang

IPC: G11C16/20 ,  G11C16/16 ,  G11C16/34

Abstract: An erase voltage compensation mechanism for group erase mode with bit line leakage detection comprises performing a block erase operation by applying an erase voltage. Continue block erasing until bit line leakage is detected upon which the erase voltage is latched and over-erase correction is performed. A compensation voltage value is calculated by finding the difference between an upper bound of a threshold voltage distribution and an erase verify point when the bit line leakage was detected. The latched erase voltage is increased by the compensation voltage to create a compensated voltage. A group erase operation is performed and the group address is incremented by 1 and the compensated voltage value is loaded. Then the group erase operation is performed on the next group. The address is incremented, the compensated voltage is loaded, and the group erase operation is performed until the group is the last group.

公开(公告)号：US20220149731A1

公开(公告)日：2022-05-12

申请号：US17092310

申请日：2020-11-08

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Che-Wei Hsu

IPC: H02M3/158 ,  H03K5/24 ,  G01R19/165 ,  H02M1/08

Abstract: A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.

公开(公告)号：US11329562B1

公开(公告)日：2022-05-10

申请号：US17092310

申请日：2020-11-08

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Che-Wei Hsu

IPC: H02M3/158 ,  H03K5/24 ,  H02M1/08 ,  G01R19/165 ,  H02M1/00

Abstract: A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.

公开(公告)号：US11265681B1

公开(公告)日：2022-03-01

申请号：US17133672

申请日：2020-12-24

Applicant: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.

Inventor： Chun-Yi Lee ,  Hung-Ta Tso ,  Chun-Chieh Huang

IPC: H04W4/029 ,  H04W4/80 ,  G01S19/26 ,  H04W4/021 ,  H04W84/12

Abstract: An electronic device is capable of determining a radio communications configuration. The electronic device includes a GPS module arranged for receiving an updated GPS coordinate. A controller is electronically coupled to the GPS module, and arranged for controlling the GPS module to receive the updated GPS coordinate and for determining the radio communications configuration based on the updated GPS coordinate received from the GPS module. A transmitter is electronically coupled to the controller and arranged for transmitting a message from the controller according to the determined radio communications configuration.