Abstract:
In order to mitigate signal reflections in a transmission interface of a display device, the present invention provides a serial transmission method for embedding data and non-data signals into transmission lines for a display device. The serial transmission method includes: obtaining a plurality of data transmission modes of the display device; defining a plurality of current patterns by a plurality of current intensities and a plurality of current directions according to the plurality of data transmission modes, each current pattern corresponding to one of the plurality of data transmission modes; and outputting one of the plurality of current patterns to an electronic device of the display device via a plurality of transmission lines according to a present data transmission mode.
Abstract:
A driving circuit of a liquid crystal display is provided. The driving circuit comprises: a plurality of gate drivers for selectively driving a plurality of thin film transistors of the liquid crystal display; a plurality of source drivers for receiving an image signal, the plurality of source drivers cooperating with the plurality of gate drivers to display an image on the liquid crystal display, each of the plurality of source drivers further comprising an adjustable common voltage generating circuit, each the adjustable common voltage generating circuit compensating, a common voltage output from each the adjustable common voltage generating circuit to make each the common voltage output from each the adjustable common voltage generating circuit the same or to make each the common voltage output to an ITO layer of a panel of the liquid crystal display the same, based on a common voltage adjustable data and a clock signal; and a timing sequence controller for providing a control signal and a data flow to the plurality of gate drivers and the plurality of source drivers and providing the common voltage adjustable data to each the adjustable common voltage generating circuit.
Abstract:
A wireless device generates a peak profile for a primary synchronization channel (PSCH), and has a synchronization stage for performing code group identification and scrambling code identification. A first peak from the peak profile is chosen. The first peak has a first path position. The synchronization stage is handed the first path position to obtain a first code group number and a first code number associated with the first peak. A multi-path search window is then opened in the peak profile around the first path position. A second peak within the multi-path search window is selected, and a verification procedure is performed on this second peak to determine if the second peak has a code number that is identical to the first code number. The first code group number is assigned to the second peak if the code number of the second peak is identical to the first code number.
Abstract:
A method of generating a smoothed transport stream to an MPEG decoder for a diversity combine digital television receiver includes generating a plurality of synchronization clocks and demodulated signals according to a plurality of digital television signals received from a plurality of antennas; monitoring a signal quality associated with each of the digital television signals; combining at least demodulated signals having a signal quality being greater than a predetermined threshold to thereby form a combined signal; generating transport stream packets according to the combined signal; selecting a synchronization signal corresponding to a digital television signal having a signal quality being greater than a second predetermined threshold as a selected synchronization signal; and generating a smoothed transport stream having packets being uniformly spaced according to the transport stream packets and the selected synchronization signal.
Abstract:
A source driver includes a data-receiving device, a data switch device, a voltage generator, a voltage switch set, a digital to analog (DAC) set, an output unit set, and a timing control device. The data-receiving device receives, registers and outputs a data signal, and the data switch set selectively outputs the data signal from the data-receiving device in response to a first timing signal. The voltage generator generates a plurality of voltages according to the reference voltages. The voltage switch set selectively outputs the voltages from the voltage generator in response to a second timing signal. The DAC set receives and outputs the selectively outputted voltages according to the selectively outputted data signal. The output unit set receives the selectively outputted voltages from the DAC and outputs an output voltage in response to a third timing signal. The timing control device provides the first, second and third timing signals.
Abstract:
A panel display apparatus and a method for driving the display panel are provided. The panel display apparatus includes a display panel and a plurality of source drivers. The display panel with X*Y display unit includes X+1 data lines, and each source driver has M+1 data output terminals DOi,j. In addition, each of the data output terminals of the source drivers is electrically coupled to a corresponding data line of the display panel, respectively. The mentioned DOi,j represents the jth data output terminal of the ith source driver. Wherein, the data output terminal DOi,M and the data output terminal DOi+1,0 are electrically coupled to a same data line of the display panel.
Abstract:
A source driver includes a data-receiving device, a data switch device, a voltage generator, a voltage switch set, a digital to analog (DAC) set, an output unit set, and a timing control device. The data-receiving device receives, registers and outputs a data signal, and the data switch set selectively outputs the data signal from the data-receiving device in response to a first timing signal. The voltage generator generates a plurality of voltages according to the reference voltages. The voltage switch set selectively outputs the voltages from the voltage generator in response to a second timing signal. The DAC set receives and outputs the selectively outputted voltages according to the selectively outputted data signal. The output unit set receives the selectively outputted voltages from the DAC and outputs an output voltage in response to a third timing signal. The timing control device provides the first, second and third timing signals.
Abstract:
A source driver having a structure of adjusting voltage with speed is suitable for use in a panel displaying apparatus for driving a display array unit. The structure of adjusting voltage with speed has a logic speed monitoring unit, an internal logic voltage generator, a substrate voltage generator, a substrate leakage-current monitoring unit, and a power management control unit. In this manner, by monitoring the logic operation speed of an internal logic circuit in the source driver, in accordance with the change of the operation frequency, the power is dynamically adjusted, so as to optimize a condition between the power consumption and the operation speed. And, in the standby mode, the power consumption is further reduced by adjusting the substrate voltage. Also and, according to the substrate leakage current of the source driver, the substrate voltage can also be adjusted.
Abstract:
Methods and systems for detecting a guard interval size in a received OFDM signal are provided. A correlation calculator calculates a preliminary correlation signal based on a digitized signal, and generates a correlation signal corresponding to each possible guard interval size by summing the preliminary correlation signal in accordance with the possible guard interval size. Characteristics such as maximum value NM and number of points above a threshold Np in a sample period for each correlation signal are determined and compared, and the actual guard interval size is selected according to the determined characteristics.
Abstract:
A source driver having the charge recycling function is suitable for a panel displaying device to drive a display array unit. The source driver includes a source driving circuit to output a plurality of data signals corresponding to a plurality of data lines. A circuit for recycling charges is coupled between the source driving circuit and the display array unit, including a plurality of switches to form a path of recycling charges and to transmit the data signals for driving the display array unit. A switch control circuit generates a set of control signals according to a timing relationship of the data signals of the circuit of source driving, to timely control the on/off states of each switch of the circuit for recycling charges. Consequently, a part of charges on the data lines can be recycled during a period of charging and discharging for the next period.