公开(公告)号：US06717441B2

公开(公告)日：2004-04-06

申请号：US10021544

申请日：2001-10-22

申请人： Atila Alvandpour ,  Per Larsson-Edefors ,  Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

发明人： Atila Alvandpour ,  Per Larsson-Edefors ,  Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

IPC分类号： H03K19096

CPC分类号： H03K3/356113 ,  H03K3/356173

摘要： A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

摘要翻译： 公开了一种具有自动切断机构的双轨静态逻辑门。 在一个实施例中，第一轨道的输出耦合到第二轨道的上拉装置的输入端，反之亦然。 交叉耦合允许静态门的自我截止机制正常工作，并提供具有比常规静态门更低的电容的组件。 较低的电容导致更快的静态栅极。

公开(公告)号：US06519178B2

公开(公告)日：2003-02-11

申请号：US10172107

申请日：2002-06-13

申请人： Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

发明人： Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

IPC分类号： G11C1140

CPC分类号： G11C11/412

摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

公开(公告)号：US06404234B1

公开(公告)日：2002-06-11

申请号：US09851917

申请日：2001-05-09

申请人： Steven K. Hsu ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

发明人： Steven K. Hsu ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.

摘要翻译： 多米诺逻辑电路和方法包括至少两个串联连接的多米诺逻辑级，每个多米诺逻辑级包括动态级和静态级。 当接收到的时钟信号和第二多米诺逻辑级的动态输出均为高电平时，第一多米诺逻辑逻辑静态级的可变虚拟接地切换到低于电路接地电平的电压电平，表明第二多米诺逻辑电路级处于评估状态 相。

公开(公告)号：US06181166B2

公开(公告)日：2001-01-30

申请号：US09099993

申请日：1998-06-19

申请人： Ram K. Krishnamurthy ,  Soumyanath Krishnamurthy

发明人： Ram K. Krishnamurthy ,  Soumyanath Krishnamurthy

IPC分类号： H03K190175

CPC分类号： H03K19/018507 ,  H03K5/151 ,  H03K19/09429

摘要： A signal driver circuit uses a single power supply to provide differential low voltage swing signals for use in an integrated circuit. The driver reduces interconnect voltage swing and power consumption, while improving the speed performance of the interconnect. The driver includes series coupled drive transistors to provide differential signals on integrated circuit interconnects. The driver circuit can include circuitry to place the interconnects in a tri-state condition to allow for shared interconnects. An integrated circuit, such as a processor, includes first and second differential interconnects, a receiver circuit connected to the first and second differential interconnects for detecting a differential voltage provided thereon, and a driver circuit connected to the first and second differential interconnects for providing the differential voltage.

摘要翻译： 信号驱动器电路使用单个电源来提供用于集成电路的差分低电压摆幅信号。 驱动器降低互连电压摆幅和功耗，同时提高互连的速度性能。 驱动器包括串联耦合的驱动晶体管，以在集成电路互连上提供差分信号。 驱动器电路可以包括将互连置于三态条件以允许共享互连的电路。 诸如处理器的集成电路包括第一和第二差分互连，连接到第一和第二差分互连用于检测其上提供的差分电压的接收器电路，以及连接到第一和第二差分互连的驱动器电路，用于提供 差分电压。