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    SYSTEM AND METHOD FOR OVER-THE-AIR ANTENNA CALIBRATION
    81.
    发明申请
    SYSTEM AND METHOD FOR OVER-THE-AIR ANTENNA CALIBRATION 有权

    公开(公告)号：US20220006185A1

    公开(公告)日：2022-01-06

    申请号：US17367175

    申请日：2021-07-02

    Applicant: Space Exploration Technologies Corp.

    Inventor： Ersin Yetisir

    IPC: H01Q3/26 ,  H04B17/12

    Abstract: An antenna calibration system for a phased array antenna in accordance with one embodiment of the present disclosure generally includes: a beamformer lattice including at least first and second beamformers, each corresponding to a subset of antenna cells, and each including a calibration section for comparing a reference signal to a non-reference signal; and a calibration antenna within the subset of antenna cells corresponding with the first beamformer, wherein the calibration antenna is configured to deliver a first reference signal (mTx) from the first beamformer to be received by a first operating antenna for comparison with a first non-reference signal (Rx) in the first beamformer or in the second beamfomer, and/or wherein the calibration antenna is configured to deliver a second non-reference signal (Tx) from a second operating antenna for comparison with a second reference signal (mRx) in the first beamformer or in the second beamformer.

    Phase lock loop (PLL) synchronization
    83.
    发明授权
    Phase lock loop (PLL) synchronization 有权

    公开(公告)号：US11133806B1

    公开(公告)日：2021-09-28

    申请号：US16858675

    申请日：2020-04-26

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

    IPC: H03L7/07 ,  H03L7/197

    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.

    Hierarchical network signal routing apparatus and method
    86.
    发明授权
    Hierarchical network signal routing apparatus and method 有权

    公开(公告)号：US10998606B2

    公开(公告)日：2021-05-04

    申请号：US16276360

    申请日：2019-02-14

    Applicant: Space Exploration Technologies Corp.

    Inventor： Souren Shamsinejad ,  Javier Rodriguez De Luis ,  Nil Apaydin ,  Alireza Mahanfar

    IPC: H01P5/19

    Abstract: In embodiments, a power splitter/combiner includes a first electrically conductive trace included in a first layer; second and third electrically conductive traces included in a second layer; a first via electrically coupled to the first and second electrically conductive traces; and a second via electrically coupled to the first and third electrically conductive traces. A first portion of the first electrically conductive trace comprises a first port of the power splitter/combiner. A second portion of the first electrically conductive trace, the first via, and the second electrically conductive trace comprises a second port of the power splitter/combiner. A third portion of the first electrically conductive trace, the second via, and the third electrically conductive trace comprises a third port of the power splitter/combiner.

    Antenna-to-beamformer assignment and mapping in phased array antenna systems
    87.
    发明授权
    Antenna-to-beamformer assignment and mapping in phased array antenna systems 有权

    公开(公告)号：US10971817B2

    公开(公告)日：2021-04-06

    申请号：US16276347

    申请日：2019-02-14

    Applicant: Space Exploration Technologies Corp.

    Inventor： Javier Rodriguez De Luis ,  Robert Baummer, Jr. ,  Nil Apaydin ,  Alireza Mahanfar

    IPC: H01Q3/30 ,  H01Q1/38 ,  H01Q3/26

    Abstract: In one embodiment of the present disclosure, a phased array antenna system includes a first portion carrying an antenna lattice including a plurality of antenna elements, wherein the plurality of antenna elements are arranged in a first configuration, a second portion carrying a beamformer lattice including a plurality of beamformer elements, wherein the plurality of beamformer elements are arranged in a second configuration different from the first configuration, and a third portion disposed between the first portion and the second portion carrying at least a portion of a mapping including a first plurality of mapping traces on a first surface providing at least a portion of the electrical connection between the plurality of antenna elements and the plurality of beamformer elements, wherein each of the plurality of antenna elements are electrically coupled to one of the plurality of beamformer elements.

    ANTENNA APPARATUS HAVING CHASSIS PORTION
    88.
    发明申请
    ANTENNA APPARATUS HAVING CHASSIS PORTION 审中-公开

    公开(公告)号：US20200381817A1

    公开(公告)日：2020-12-03

    申请号：US16892239

    申请日：2020-06-03

    Applicant: Space Exploration Technologies Corp.

    Inventor： Duncan E. Adams ,  David Milroy

    IPC: H01Q1/42 ,  H01Q1/12 ,  H01Q1/02 ,  H01Q9/04

    Abstract: In one embodiment of the present disclosure, a housing for an antenna system having a plurality of antenna elements defining an antenna aperture includes a chassis portion having an internal support portion for internal components for the plurality of antenna elements including a bonding portion for bonding an antenna stack assembly to the chassis portion, and a radome portion configured for coupling to the chassis portion to define an inner chassis chamber.

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