公开(公告)号：US06442100B2

公开(公告)日：2002-08-27

申请号：US09904358

申请日：2001-07-12

申请人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

发明人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

IPC分类号： G11C800

CPC分类号： G11C7/06 ,  G11C7/1048 ,  G11C11/22

摘要： The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

摘要翻译： 集成存储器具有通过开关元件连接到读写放大器的输入的m≥1位线。 每个读或写访问只有一个开关元件被导电连接。 存储器设置有影响通过读写放大器和位线发生的读取或写入访问的切换单元。 电路单元具有激活输入。 列端解码器具有第一解码器级和m个第二解码器级。 第二解码器级的输出端连接到每个开关元件的控制输入端。 第一解码器级的输出连接到开关单元的启动输入。