公开(公告)号：US5764929A

公开(公告)日：1998-06-09

申请号：US573681

申请日：1995-12-18

申请人： Richard Allen Kelley ,  Danny Marvin Neal

发明人： Richard Allen Kelley ,  Danny Marvin Neal

IPC分类号： G06F13/12 ,  G06F13/368 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/126 ,  G06F13/368 ,  G06F13/4059

摘要： The present invention accomplishes bus utilization optimization by enabling each device to signal another bus device when it has completion information in its output buffers. For example, when an I/O device attempts to read data from a system device, a RETRY may be signalled to the requesting I/O device. A control signal is sent from the bridge to the requesting I/O device when there is completion data in its output buffers. In this manner, the present invention eliminates or reduces the multiple RETRY actions by the I/O device, since it will not attempt to obtain the data until it receives the control signal from the bridge.

摘要翻译： 本发明通过使每个设备在其输出缓冲器中具有完成信息时使另一总线设备发信号来实现总线利用优化。 例如，当I / O设备尝试从系统设备读取数据时，可以向请求的I / O设备发信号通知RETRY。 当输出缓冲器中有完成数据时，控制信号从桥接器发送到请求的I / O设备。 以这种方式，本发明消除或减少了I / O设备的多个RETRY动作，因为在从桥接收到控制信号之前，它不会尝试获取数据。

公开(公告)号：US5761461A

公开(公告)日：1998-06-02

申请号：US766735

申请日：1996-12-13

申请人： Danny Marvin Neal ,  Steven Mark Thurber

发明人： Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： A method for preventing peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, denying the access request such that a PCI peer-to-peer access across separate PCI host bridges within a data processing system is prevented.

摘要翻译： 描述了用于防止在数据处理系统内的分开的外围组件互连（PCI）主机桥的对等访问的方法。 根据本发明的方法和系统，在来自PCI设备的访问请求期间，首先确定访问请求是否用于连接到系统总线的系统存储器。 响应于确定访问请求不是连接到系统总线的系统存储器，则另外确定访问请求是否用于与请求的PCI设备相同的PCI主机桥下的PCI设备。 响应于确定访问请求不是针对与请求的PCI设备相同的PCI主机桥下的PCI设备，拒绝访问请求，使得跨数据处理中的单独PCI主机桥的PCI对等访问 系统被阻止。

公开(公告)号：US5673399A

公开(公告)日：1997-09-30

申请号：US552034

申请日：1995-11-02

申请人： Guy Lynn Guthrie ,  Danny Marvin Neal ,  Edward John Silha ,  Steven Mark Thurber

发明人： Guy Lynn Guthrie ,  Danny Marvin Neal ,  Edward John Silha ,  Steven Mark Thurber

IPC分类号： G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the host bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions based on the protocol of the buses being interconnected through the bridge.

摘要翻译： 数据处理系统包括主处理器，多个外围设备以及可以在主机，外围设备和其他主机或诸如网络中的外围设备之间连接的一个或多个网桥。 每个桥梁（如PCI主机桥）连接在主总线（例如系统总线）和辅助总线之间，为了清楚起见，主总线将被视为出站事务的来源和入站事务的目的地， 辅助总线将被视为出站交易的目的地和入站交易的来源。 主桥包括出站数据路径，入站数据路径和控制机制。 出站数据路径包括排队缓冲器，用于按照从主总线接收的顺序存储事务，其中排队缓冲器中的请求可以在读请求和写事务之间混合，出站路径还包括多个用于存储读取的并行缓冲器 回复数据和地址信息。 入站路径是出站路径的镜像，读取请求和写入请求存储在顺序缓冲区中，并且读取回复存储在多个并行缓冲区中。 主桥中的入站路径和出站路径都由状态机控制，该状态机考虑到两个方向的活动，并且基于通过桥互连的总线的协议允许或禁止旁路交易。