ARRAY OF INTEGRATED PIXEL AND MEMORY CELLS FOR DEEP IN-SENSOR, IN-MEMORY COMPUTING

    公开(公告)号:US20210173894A1

    公开(公告)日:2021-06-10

    申请号:US16705434

    申请日:2019-12-06

    Abstract: Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.

    Waveguide bends with mode confinement

    公开(公告)号:US10989872B1

    公开(公告)日:2021-04-27

    申请号:US16657291

    申请日:2019-10-18

    Abstract: Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A waveguide bend is connected to a waveguide core. A slab layer, which is thinner than the waveguide bend, is coupled to the waveguide core and the waveguide bend. The slab layer includes a first curved opening and a second curved opening that is positioned between the first curved opening and a side surface of the waveguide bend. A section of the slab layer is positioned between the first and second curved openings. The first curved opening has a first radius, and the second curved opening has a second radius that is greater than or less than the first radius of the first curved opening.

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