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公开(公告)号：US10901744B2
公开(公告)日：2021-01-26
申请号：US15826741
申请日：2017-11-30
摘要： Aspects of the invention include buffered instruction dispatching to an issue queue. A non-limiting example includes dispatching from a dispatch unit of a processor a first group of instructions selected from a first plurality of instructions to a first issue queue partition of the processor in a first cycle. A second group of instructions selected from the first plurality of instructions is passed to an issue queue buffer of the processor in the first cycle. The second group of instructions is passed from the issue queue buffer to the first issue queue partition in a second cycle. A third group of instructions selected from a second plurality of instructions is dispatched to a second issue queue partition in the second cycle.
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82.发明授权公开(公告)号：US10802829B2
公开(公告)日：2020-10-13
申请号：US15826742
申请日：2017-11-30
IPC分类号： G06F9/38
摘要： Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, tracking a specific dependency on each of a threshold number of instructions most recently added to the issue queue prior to the instruction, tracking as a single group a dependency of the instruction on any instructions in the issue queue that are not in the threshold number of instructions, and tracking for each source register used by the instruction an indicator of whether its content is dependent on results from an instruction in the single group that has not finished execution. Based at least in part on detecting removal from the issue queue of an instruction in the single group that has issued and not finished execution, the method includes indicating that the instruction is ready for issuance or waiting for a notification that the removed instruction has finished execution.
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公开(公告)号：US10564979B2
公开(公告)日：2020-02-18
申请号：US15826752
申请日：2017-11-30
摘要： Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.
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公开(公告)号：US10481915B2
公开(公告)日：2019-11-19
申请号：US15709740
申请日：2017-09-20
发明人： Bryan J. Lloyd , Balaram Sinharoy
IPC分类号： G06F9/38 , G06F12/0846 , G06F12/0875 , G06F9/30
摘要： Provided are methods, systems, and computer program products to implementing a split store data queue for an out-of-order (OoO) processor. A non-limiting example of the computer-implemented method includes detecting, by the OoO processor, a mode of the OoO processor. The method further includes partitioning, by the OoO processor, a first store data queue (SDQ) and a second SDQ based at least in part on the mode of the OoO processor. The method further includes receiving, by the OoO processor, a vector operand. The method further includes storing, by the OoO processor, the vector operand in at least one of the first SDQ and the second SDQ based at least in part on the mode of the OoO processor.
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85.发明授权公开(公告)号：US10394558B2
公开(公告)日：2019-08-27
申请号：US15726639
申请日：2017-10-06
摘要： Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.
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公开(公告)号：US20190163486A1
公开(公告)日：2019-05-30
申请号：US15826745
申请日：2017-11-30
摘要： Aspects include monitoring a number of instructions of a first type dispatched to a first shared port of an issue queue of a processor and determining whether the number of instructions of the first type dispatched to the first shared port exceeds a port selection threshold. An instruction of a third type is dispatched to a second shared port of the issue queue associated with a plurality of instructions of a second type based on determining that the number of instructions of the first type dispatched to the first shared port exceeds the port selection threshold. The instruction of the third type is dispatched to the first shared port of the issue queue associated with a plurality of instructions of the first type based on determining that the number of instructions of the first type dispatched to the first shared port does not exceed the port selection threshold.
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公开(公告)号：US20190163482A1
公开(公告)日：2019-05-30
申请号：US15826734
申请日：2017-11-30
IPC分类号： G06F9/38
摘要： Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of a threshold number of instructions. A dependency between the instruction and the other instructions is tracked as a single group by indicating that a dependency exists between the instruction and the group of other instructions based on identifying a dependency between the instruction and at least one of the other instructions in the single group. Instructions are issued from the issue queue based at least in part on the tracking.
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88.发明申请公开(公告)号：US20190108028A1
公开(公告)日：2019-04-11
申请号：US15825625
申请日：2017-11-29
IPC分类号： G06F9/30 , G06F9/38 , G06F9/32 , G06F12/1009
摘要： Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.
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公开(公告)号：US20190108021A1
公开(公告)日：2019-04-11
申请号：US15726522
申请日：2017-10-06
发明人： Bryan Lloyd , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F12/1027 , G06F12/122 , G06F12/1009 , G06F12/1045 , G06F12/0862 , G06F12/128
摘要： Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit. An example method includes looking up, by a load-store unit (LSU), an entry in an effective address directory (EAD) for an effective address (EA) of an operand of an instruction to be launched. Further, the method includes, in response to the EA being present in the EAD, launching, by the LSU, the instruction with the RA from the EAD, and in response to the EA not being present in the EAD, looking up, by the LSU, the EA in an effective real table (ERT) entry, and launching the instruction with the RA from the ERT entry. Further, in response to the ERT entry to be removed, the ERT entry including an ERT index and a mapping between the EA and the RA, removing the entry of the EA from the EAD.
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90.发明申请公开(公告)号：US20190087196A1
公开(公告)日：2019-03-21
申请号：US15709777
申请日：2017-09-20
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/34 , G06F9/3804
摘要： Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes fetching, by an instruction fetch unit, a first instruction from an instruction cache. The method further includes associating, by an effective address table logic, an entry in an effective address table (EAT) with the first instruction. The method further includes fetching, by the instruction fetch unit, a second instruction from the instruction cache, wherein the first instruction occurs before a branch has been taken and the second instruction occurs after the branch has been taken. The method further includes associating at least a portion of the entry in the EAT associated with the first instruction in response to the second instruction utilizing a cache line utilized by the first instruction and processing the first instruction and the second instruction through a processor pipeline utilizing the entry of the EAT.
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