公开(公告)号：US08856720B2

公开(公告)日：2014-10-07

申请号：US13733248

申请日：2013-01-03

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

IPC: G06F11/22 ,  G06F17/50

CPC classification number: G01R31/3177 ,  G01R31/318566 ,  G01R31/3193 ,  G06F17/50

Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.

Abstract translation: 公开了一种在半导体芯片上定位故障逻辑的方法。 该方法可以包括确定包含一个或多个逻辑元件的半导体芯片的故障率。 该方法还可以包括使用故障率来确定掩蔽图案。 使用确定方法，掩模图案可以掩蔽小于所有逻辑元件。 该方法还可以包括将测试向量应用于所选择的逻辑元件，其中来自测试向量的结果与参考值进行比较。