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公开(公告)号：US06939726B2
公开(公告)日：2005-09-06
申请号：US10634005
申请日：2003-08-04
Applicant: Yung-Lung Hsu , James Wu
Inventor： Yung-Lung Hsu , James Wu
IPC: H01L21/66 , H01L23/544 , G01R31/26 , H01L21/4763
CPC classification number: H01L22/20 , H01L22/34 , H01L2924/3011 , Y10S438/926
Abstract: An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via array including a plurality of interspersed electrically isolated dummy metal portions to form a via array monitor; exposing the semiconductor process wafer including the via array monitor to an electrical charge altering process including to produce an electrically charged state over at least a portion of the semiconductor wafer; carrying out electrical measurements of the via array monitor to determine a level of the electrically charged state; and, carrying out an electrically charge neutralizing process to reduce a level of the electrically charged state to a predetermined acceptable level prior to carrying out a subsequent process.
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公开(公告)号：US06555435B2
公开(公告)日：2003-04-29
申请号：US10087070
申请日：2002-03-01
Applicant: Ming-Hsiung Chiang , James Wu , Yu-Hua Lee
Inventor： Ming-Hsiung Chiang , James Wu , Yu-Hua Lee
IPC: H01L2336
CPC classification number: H01L21/76831 , H01L21/76897
Abstract: A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.
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Patent Agency Ranking
85.发明授权Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids 有权消除由于层间电介质空隙引起的相邻触点之间的短路的方法公开(公告)号：US06365464B1
公开(公告)日：2002-04-02
申请号：US09318470
申请日：1999-05-25
Applicant: Ming-Hsiung Chiang , James Wu , Yu-Hua Lee
Inventor： Ming-Hsiung Chiang , James Wu , Yu-Hua Lee
IPC: H10L21336
CPC classification number: H01L21/76831 , H01L21/76897
Abstract: A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.
Abstract translation: 在集成电路器件中形成接触的方法包括消除由于电介质层空隙引起的相邻触点之间的短路。 提供基板。 在基板上设置窄间隔的导线。 沉积覆盖导电线和衬底的电介质层。 在由光刻掩模限定的区域中，将介电层蚀刻到衬底的顶表面，以在相邻的窄间隔的导线之间形成接触开口。 绝缘层沉积在电介质层上方并填充接触开口，其中绝缘层在接触开口内形成衬里层，并填充延伸出接触开口的电介质层中的任何空隙。 蚀刻绝缘层以暴露衬底的顶表面。 沉积覆盖介电层并填充接触开口的导电层。 如由光刻掩模所限定的那样蚀刻导电层。 沉积覆盖在导电层和电介质层上的钝化层。 集成电路装置完成。
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公开(公告)号：US6100116A
公开(公告)日：2000-08-08
申请号：US99144
申请日：1998-06-18
Applicant: Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
Inventor： Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
IPC: H01L23/525 , H01L21/82
CPC classification number: H01L23/5258 , H01L2924/0002
Abstract: A method for forming protection layers completely around a metal fuse to protect the metal fuse 74A and metal lines 74B from moisture corrosion from fuse opening and micro-cracks in dielectric layers. The invention surrounds the fuse on all sides with two protection layers: a bottom protection layer 70 and a top protection layer 78. The top protection layer 78 is formed over the fuse metal, the sidewalls of the metal fuse and the bottom protection layer 70. The protection layers 70 78 of the invention form a moisture proof seal structure around the metal fuse 74A and protect the metal fuse 74A and metal lines 74B from moisture and contaminates.
Abstract translation: 一种用于在金属保险丝周围完全形成保护层的方法，用于保护金属保险丝74A和金属线74B免受保险丝开口的湿度腐蚀和电介质层中的微裂纹。 本发明在所有侧面上具有两个保护层的保险丝：底部保护层70和顶部保护层78.顶部保护层78形成在熔丝金属，金属熔断器的侧壁和底部保护层70上。 本发明的保护层70 78在金属熔断器74A周围形成防潮密封结构，并且保护金属熔断器74A和金属线74B免受潮湿和污染。
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