公开(公告)号：US20180047846A1

公开(公告)日：2018-02-15

申请号：US15730542

申请日：2017-10-11

申请人： INTEL CORPORATION

发明人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H04B1/3827 ,  H01L29/06 ,  H01L29/10 ,  H01L29/267

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US20180006048A1

公开(公告)日：2018-01-04

申请号：US15691136

申请日：2017-08-30

申请人： Renesas Electronics Corporation

发明人： Keisuke TSUKAMOTO ,  Tatsuyoshi MIHARA

IPC分类号： H01L27/11531 ,  H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11563 ,  H01L27/11521 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51

CPC分类号： H01L27/11531 ,  H01L21/265 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11521 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S438/926

摘要： A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

公开(公告)号：US20160197185A1

公开(公告)日：2016-07-07

申请号：US15069726

申请日：2016-03-14

申请人： INTEL CORPORATION

发明人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H04B1/3827 ,  H01L29/267 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/24

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US08214776B2

公开(公告)日：2012-07-03

申请号：US13153764

申请日：2011-06-06

申请人： Katsumi Mori ,  Kei Kawahara ,  Yoshikazu Kasuya

发明人： Katsumi Mori ,  Kei Kawahara ,  Yoshikazu Kasuya

IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L31/00 ,  H01L27/088

CPC分类号： H01L27/0207 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

摘要翻译： 半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32.半导体器件限定行方向，并且沿着穿过第一布线层30的方向延伸的第一虚拟线性线L1 行方向。 行方向和第一虚拟线性线L1限定2-40度的角度，并且虚设布线层32以位于第一虚拟线性线L1上的方式设置。 半导体器件还限定垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线L2。 列方向和第二虚拟线性线L2限定2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L2上的方式设置。

公开(公告)号：US08110875B2

公开(公告)日：2012-02-07

申请号：US12166362

申请日：2008-07-02

申请人： John Joseph Ellis-Monaghan ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Steven Howard Voldman

发明人： John Joseph Ellis-Monaghan ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Steven Howard Voldman

IPC分类号： H01L23/62

CPC分类号： H01L27/0248 ,  Y10S438/926

摘要： A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

摘要翻译： 用于在集成电路制造期间耗散电荷的结构。 该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

公开(公告)号：US08021942B2

公开(公告)日：2011-09-20

申请号：US12049548

申请日：2008-03-17

申请人： Andy Wei ,  Andrew Waite ,  Martin Trentzsch ,  Johannes Groschopf ,  Gunter Grasshoff ,  Andreas Ott

发明人： Andy Wei ,  Andrew Waite ,  Martin Trentzsch ,  Johannes Groschopf ,  Gunter Grasshoff ,  Andreas Ott

IPC分类号： H01L21/8238 ,  H01L21/70 ,  H01L27/092

CPC分类号： H01L21/82345 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/926

摘要： In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.

摘要翻译： 在通过高k金属栅极结构代替常规栅电极结构的工艺顺序中，例如通过使用高选择性蚀刻步骤，附加掩模步骤的数量可以保持在低水平，从而保持与常规栅极结构的高度兼容性 CMOS技术。 此外，本文公开的技术使得能够与前端处理技术和后端处理技术兼容，从而允许将已建立的应变诱发机制集成在晶体管级以及接触级中。

公开(公告)号：US20110156145A1

公开(公告)日：2011-06-30

申请号：US13042973

申请日：2011-03-08

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

IPC分类号： H01L29/78

CPC分类号： H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

摘要翻译： 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许在沟道区下方除去氧化物。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

公开(公告)号：US07964487B2

公开(公告)日：2011-06-21

申请号：US12132887

申请日：2008-06-04

申请人： Kangguo Cheng ,  Haining S Yang

发明人： Kangguo Cheng ,  Haining S Yang

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7845 ,  Y10S438/926

摘要： An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

摘要翻译： 提供了具有应力增强通道的集成电路，设计结构和制造集成电路的方法。 该方法包括在衬底上形成虚拟栅极结构并在虚拟栅极结构中形成沟槽。 该方法还包括用应变诱导材料填充沟槽的一部分并用栅极材料填充沟槽的剩余部分。

公开(公告)号：US20110095363A1

公开(公告)日：2011-04-28

申请号：US12982101

申请日：2010-12-30

申请人： Matthew Currie ,  Anthony Lochtefeld ,  Richard Hammond ,  Eugene Fitzgerald

发明人： Matthew Currie ,  Anthony Lochtefeld ,  Richard Hammond ,  Eugene Fitzgerald

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L29/105 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7842 ,  Y10S438/926

摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

摘要翻译： 包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。 应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。 当杂质存在于应变材料层的某些区域中时，器件性能下降。 通过采用具有所描述或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

公开(公告)号：US07888195B2

公开(公告)日：2011-02-15

申请号：US12198128

申请日：2008-08-26

申请人： Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

发明人： Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S438/926

摘要： A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.

摘要翻译： 公开了一种用于制造具有金属栅极的晶体管的方法。 首先，提供衬底，其中衬底包括第一晶体管区域和第二晶体管区域。 在基板上形成多个虚拟栅极，在虚拟栅极上淀积介质层。 去除虚拟栅极以在电介质层中形成多个开口。 形成高k电介质层以覆盖电介质层和开口的表面，此后在高k电介质层上形成覆盖层。 去除设置在第二晶体管区域中的盖层，并且在第一晶体管区域的盖层和第二晶体管区域的高k电介质层上沉积金属层。 形成导电层以填充第一晶体管区域和第二晶体管区域的开口。