公开(公告)号：US20100106893A1

公开(公告)日：2010-04-29

申请号：US12414925

申请日：2009-03-31

申请人： Luca Fasoli ,  Yuheng Zhang ,  Gopinath Balakrishnan

发明人： Luca Fasoli ,  Yuheng Zhang ,  Gopinath Balakrishnan

IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F12/00

CPC分类号： G11C16/102 ,  G06F12/0246

摘要： A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.

摘要翻译： 一种用于在与外部主机设备通信的存储设备中有效地处理写入操作故障的技术允许从页面缓冲器将数据页面重写到存储器阵列。 主机向存储设备提供用户数据，第一写地址和写命令。 如果写入尝试失败，则主机提供具有新地址的重写命令，而不会将用户数据重新发送到存储设备。 在来自页面缓冲器的重新写入正在进行时，可以在存储器件的数据高速缓存处接收附加数据。 重新写入的数据可以在数据被读出到主机的复制操作中获得，被修改并写回存储器件。 在复制操作期间可以向存储器件输入附加数据。 页面缓冲区数据也可以进行修改。

公开(公告)号：US20100085822A1

公开(公告)日：2010-04-08

申请号：US12563140

申请日：2009-09-20

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.

摘要翻译： 非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开 信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时 信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。 对控制线进行充电导致相应的非易失性存储元件经历程序操作。 在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

公开(公告)号：US20100046267A1

公开(公告)日：2010-02-25

申请号：US12410648

申请日：2009-03-25

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C5/02 ,  G11C8/00 ,  G11C5/06

CPC分类号： G11C16/24 ,  G11C13/0028

摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

摘要翻译： 存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。 块被分组成海湾。 存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。 每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。 该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。 每个一个或多个块的集合包括一组本地数据线。 每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。 每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。 每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。