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公开(公告)号：US20240194255A1
公开(公告)日：2024-06-13
申请号：US18065046
申请日：2022-12-13
IPC分类号： G11C13/00 , H01L23/522 , H01L27/105 , H01L29/417
CPC分类号： G11C13/0007 , H01L23/5226 , H01L27/1052 , H01L29/41725 , G11C2213/34 , G11C2213/52
摘要： The disclosed subject matter relates generally to structures for use in memory devices. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having source, drain, and control electrodes. The present disclosure provides a memory structure including a source electrode, a drain electrode, a control electrode laterally between the source electrode and the drain electrode, a hole generating layer above the control electrode, a dielectric channel layer above the hole generating layer, the dielectric channel layer contacts the source electrode and the drain electrode, a first spacer layer on a first side of the control electrode, and a second spacer layer on a second side of the control electrode. The first spacer layer and the second spacer layer isolate the source electrode and the drain electrode from the control electrode and the hole generating layer.
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2.发明授权公开(公告)号：US11967376B2
公开(公告)日：2024-04-23
申请号：US17899356
申请日：2022-08-30
申请人： CROSSBAR, INC.
发明人： Sung Hyun Jo , Hagop Nazarian , Sang Nguyen , Jeremy Guy , Zhi Li
CPC分类号： G11C13/0059 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0069 , H04L9/3278 , H10B63/80 , H10N70/24 , H10N70/801 , H10N70/841 , G11C2013/0045 , G11C2013/0078 , G11C2013/0088
摘要： Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.
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公开(公告)号：US11963465B2
公开(公告)日：2024-04-16
申请号：US18114419
申请日：2023-02-27
发明人： Zhichao Lu , Gary Bela Bronner
CPC分类号： H10N70/24 , G11C13/0007 , G11C13/0011 , H10N70/021 , H10N70/041 , H10N70/245 , H10N70/826 , H10N70/841 , H10N70/881 , H10N70/8825 , H10N70/8833 , G11C2213/50 , G11C2213/51
摘要： Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.
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4.发明公开公开(公告)号：US20240112730A1
公开(公告)日：2024-04-04
申请号：US17957945
申请日：2022-09-30
申请人： Intel Corporation
发明人： Sou-Chi Chang , Nazila Haratipour , Saima Siddiqui , Uygar Avci , Chia-Ching Lin
CPC分类号： G11C13/0026 , G11C11/22 , G11C13/0007 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C13/0069 , H01L45/1233 , H01L45/1253 , H01L45/146 , G11C2213/79
摘要： Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.
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公开(公告)号：US11923289B2
公开(公告)日：2024-03-05
申请号：US17837923
申请日：2022-06-10
发明人： Sanh D. Tang , Roger W. Lindsay , Krishna K. Parat
IPC分类号： H01L23/52 , G11C13/00 , H01L23/528 , H01L27/10 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B63/00 , H10N70/00
CPC分类号： H01L23/52 , G11C13/0007 , H01L23/528 , H01L27/10 , H01L27/101 , H10B41/27 , H10B43/27 , H10B43/35 , H10B63/845 , H10N70/8822 , H10N70/8825 , H10N70/8828 , H10N70/8833 , H10N70/8836 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75 , H01L2924/0002 , H10B41/35 , H10N70/882 , H10N70/883 , H01L2924/0002 , H01L2924/00
摘要： A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.
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公开(公告)号：US11886972B2
公开(公告)日：2024-01-30
申请号：US17036490
申请日：2020-09-29
申请人： Arm Limited
IPC分类号： G06N3/04 , G11C13/00 , G06F7/544 , H03M1/12 , H03M1/66 , G06N3/065 , G06N3/045 , G06N3/048 , G11C11/54 , G06N3/044
CPC分类号： G06N3/04 , G06F7/5443 , G06N3/045 , G06N3/048 , G06N3/065 , G11C11/54 , G11C13/0007 , G11C13/0069 , G06N3/044 , H03M1/12 , H03M1/66
摘要： A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.
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公开(公告)号：US11871587B2
公开(公告)日：2024-01-09
申请号：US18054075
申请日：2022-11-09
申请人： SK hynix Inc.
发明人： Hyung Dong Lee
IPC分类号： H10B63/00 , H01L23/522 , H01L23/528 , H10N70/00 , G11C13/00
CPC分类号： H10B63/84 , H01L23/528 , H01L23/5226 , H10B63/30 , G11C13/0007 , G11C13/0026 , H10B63/20 , H10N70/8833
摘要： A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.
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公开(公告)号：US11848050B2
公开(公告)日：2023-12-19
申请号：US17829571
申请日：2022-06-01
CPC分类号： G11C13/0069 , G11C13/004 , G11C13/0007 , G11C13/0028 , G11C13/0097 , G11C8/08 , G11C2013/0045 , G11C2013/0071 , G11C2013/0078 , G11C2213/79
摘要： The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
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公开(公告)号：US11825665B2
公开(公告)日：2023-11-21
申请号：US17949436
申请日：2022-09-21
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L29/78 , H10B99/00 , H01L27/105 , H01L27/12 , H10B12/00 , H10B41/20 , H10B41/70 , H01L29/24 , H01L29/786 , G11C13/00 , H01L49/02 , H10B10/00
CPC分类号： H10B99/00 , H01L27/105 , H01L27/124 , H01L27/1225 , H01L27/1255 , H01L29/24 , H01L29/7869 , H01L29/78696 , H10B12/00 , H10B41/20 , H10B41/70 , G11C13/003 , G11C13/0007 , G11C2213/79 , H01L28/40 , H10B10/00
摘要： An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.
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公开(公告)号：US11817148B2
公开(公告)日：2023-11-14
申请号：US17685219
申请日：2022-03-02
CPC分类号： G11C13/0069 , G11C5/063 , G11C13/004 , G11C13/0007 , G11C13/0064 , G11C2013/009 , G11C2013/0073
摘要： Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
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