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    Selective message processing by external processors for network data storage devices
    81.
    发明授权
    Selective message processing by external processors for network data storage devices 有权

    公开(公告)号：US11775225B1

    公开(公告)日：2023-10-03

    申请号：US17866353

    申请日：2022-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Luca Bert

    IPC: G06F3/06

    CPC classification number: G06F3/067 ,  G06F3/0605 ,  G06F3/0632 ,  G06F3/0656

    Abstract: A storage product manufactured as a computer component to facilitate network storage services. The storage product has a bus connector, a network interface, and a local storage device. A message selection configuration can be written into the storage product to control separation of incoming messages received in the network interface into first messages and third messages. The first messages are sent through the bus connector for processing by a local host system to generate second messages. The second messages and the third messages are sent to the local storage device. The local storage device processes the second messages and the third messages to implement the network storage services.

    Managing capacity reduction and recovery due to storage device failure
    84.
    发明授权
    Managing capacity reduction and recovery due to storage device failure 有权

    公开(公告)号：US11520656B2

    公开(公告)日：2022-12-06

    申请号：US17207432

    申请日：2021-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Luca Bert

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14 ,  G06F3/06 ,  G06F11/32

    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.

    MEMORY SUB-SYSTEMS INCLUDING MEMORY DEVICES OF VARIOUS LATENCIES AND CAPACITIES
    85.
    发明申请
    MEMORY SUB-SYSTEMS INCLUDING MEMORY DEVICES OF VARIOUS LATENCIES AND CAPACITIES 有权

    公开(公告)号：US20220019379A1

    公开(公告)日：2022-01-20

    申请号：US16933755

    申请日：2020-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Luca Bert

    IPC: G06F3/06 ,  G06F12/1009

    Abstract: A write request comprising a logical address, a payload, and an indicator reflecting the character of the payload is received from an application. Based on the indicator, a value of a parameter associated with storing the payload on one or more of a plurality of memory devices is identified. The value of the parameter is determined to satisfy a criterion associated with a particular memory device of the plurality of memory devices. The payload is stored on the particular memory device.

    MEMORY CACHE MANAGEMENT BASED ON STORAGE CAPACITY FOR PARALLEL INDEPENDENT THREADS
    86.
    发明申请
    MEMORY CACHE MANAGEMENT BASED ON STORAGE CAPACITY FOR PARALLEL INDEPENDENT THREADS 有权

    公开(公告)号：US20220012176A1

    公开(公告)日：2022-01-13

    申请号：US16922959

    申请日：2020-07-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luca Bert

    IPC: G06F12/0808

    Abstract: A request to write a first data item associated with a first thread to a memory device is received. The memory device includes a first portion and a second portion. The first portion includes a cache that includes a first block to be utilized for data caching and a second block and a third block to be used for block compaction. The second block is associated with a high modification frequency and the third block is associated with a low modification frequency. In response to determining a first memory page in the first block is available for writing the first data item, the first data item is written to the first memory page. A determination is made that a memory page criterion associated with the first thread has been satisfied. In response to identifying each of a set of second memory pages associated with the first thread written to at least one of the second block or the third block, the data of first memory page and each of the set of second memory pages is copied to the second portion of the memory device. The first memory page is marked as invalid on the first block and each of the set of second memory pages associated with the first thread are marked as invalid on at least one of the second block or the third block.

    STORING ZONES IN A ZONE NAMESPACE ON SEPARATE PLANES OF A MULTI-PLANE MEMORY DEVICE
    87.
    发明申请
    STORING ZONES IN A ZONE NAMESPACE ON SEPARATE PLANES OF A MULTI-PLANE MEMORY DEVICE 有权

    公开(公告)号：US20210405898A1

    公开(公告)日：2021-12-30

    申请号：US17447513

    申请日：2021-09-13

    Applicant: Micron Technology, Inc.

    Inventor： Luca Bert

    IPC: G06F3/06

    Abstract: A processing device in a memory system receives requests to perform a plurality of memory access operations at a memory device configured with a zone namespace having a plurality of zones, the memory device comprising a plurality of planes, wherein each zone of the plurality of zones is associated with a respective plane of the plurality of planes. The processing device further concurrently performs the plurality of memory access operations on data stored in different zones of the plurality of zones, wherein the different zones are associated with different planes of the plurality of planes.

    QUALITY OF SERVICE FOR MEMORY DEVICES USING WEIGHTED MEMORY ACCESS OPERATION TYPES
    89.
    发明申请
    QUALITY OF SERVICE FOR MEMORY DEVICES USING WEIGHTED MEMORY ACCESS OPERATION TYPES 有权

    公开(公告)号：US20210124497A1

    公开(公告)日：2021-04-29

    申请号：US16663029

    申请日：2019-10-24

    Applicant: Micron Technology, Inc.

    Inventor： Luca Bert

    IPC: G06F3/06

    Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, a function of the plurality of functions receives input/output (I/O) operations from a host computing system. The processing device further selects a first function of the plurality of functions to service and assigns a first operation weight to a first I/O operation type of I/O operations received at the first function and a second operation weight to a second I/O operation type of I/O operations received at the first function. The processing device also selects, for execution, a first number of operations of the first I/O operation type of the I/O operations received at the first function according to the first operation weight and a second number of operations of the second I/O operation type of the I/O operations received at the first function according to the second operation weight. The processing device then executes the first number of operations and the second number of operations at the memory device.

    Combined cryptographic key management services for access control and proof of space
    90.
    发明授权
    Combined cryptographic key management services for access control and proof of space 有权

    公开(公告)号：US12301713B2

    公开(公告)日：2025-05-13

    申请号：US18743476

    申请日：2024-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Luca Bert ,  Joseph Harold Steinmetz

    IPC: H04L9/08 ,  G06F3/06 ,  H04L9/30 ,  G06F21/60 ,  G06F21/79 ,  H04L9/00 ,  H04L9/32

    Abstract: A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.

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