公开(公告)号：US11048636B2

公开(公告)日：2021-06-29

申请号：US16528474

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/0864 ,  G06F13/16 ,  G06F9/30 ,  G06F9/38

Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

公开(公告)号：US20210157741A1

公开(公告)日：2021-05-27

申请号：US17170763

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/1009 ,  G06F12/14 ,  G06F9/455 ,  G06F21/53 ,  G11C11/408

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing security settings for calls from predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a call to execute a routine identified using the virtual memory address, a security setting corresponding to the execution domain from which the call initiates can be extracted from the page table entry to determine whether a security measure is to be used. For example, a shadow stack structure can be used to protect the private stack content of the routine from being access by a caller and/or to protect the private stack content of the caller from being access by the callee.

公开(公告)号：US20210034366A1

公开(公告)日：2021-02-04

申请号：US16528479

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0842

Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.

公开(公告)号：US20200371886A1

公开(公告)日：2020-11-26

申请号：US16417526

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F11/26 ,  G06F11/22 ,  G06F9/30

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

公开(公告)号：US20200301875A1

公开(公告)日：2020-09-24

申请号：US16356146

申请日：2019-03-18

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F15/80 ,  G06F9/30 ,  G06F7/57

Abstract: A vector processor with a vector first and multi-lane configuration. A vector operation for a vector processor can include a single vector or multiple vectors as input. Multiple lanes for the input can be used to accelerate the operation in parallel. And, a vector first configuration can enhance the multiple lanes by reducing the number of elements accessed in the lanes to perform the operation in parallel.

公开(公告)号：US10761855B2

公开(公告)日：2020-09-01

申请号：US16028750

申请日：2018-07-06

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

公开(公告)号：US20200073694A1

公开(公告)日：2020-03-05

申请号：US16520310

申请日：2019-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/455

Abstract: Systems, apparatuses, and methods related to a virtual machine register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store, in the virtual machine register, an identifier of a virtual machine for which the processor is currently executing instructions in a current domain in the set of domains. For example, the processor can implement resource restriction/mapping and/or perform address translation for the virtual machine based on the identifier stored in the virtual machine register.

公开(公告)号：US20200073693A1

公开(公告)日：2020-03-05

申请号：US16520304

申请日：2019-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/455 ,  G06F13/10 ,  G06F9/48 ,  G06F12/1009

Abstract: Systems, apparatuses, and methods related to a hypervisor status register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store a value in the hypervisor status register during a power up process of the computer system. The value stored in the hypervisor status register that identifies whether or not an operating hypervisor is present in the computer system. The computer processor can configure its operations (e.g., address translation) based on the value stored in the hypervisor status register.

公开(公告)号：US20200042745A1

公开(公告)日：2020-02-06

申请号：US16054913

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/71 ,  G06F9/30 ,  G06F21/60 ,  G06F12/0802 ,  G06F12/14

Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a cache, a register, an execution unit, and an unscrambler. The processor can load the scrambled data into the cache; and the unscrambler may convert the scrambled data into unscrambled data just in time for the register or the execution unit during instruction execution. The unscrambled data can be an instruction, an address, or an operand of an instruction. Unscrambling can be performed just before loading the data item in a scrambled form from the cache into the register in an unscrambled form, or after the data item leaves the register in the scrambled form as input to the execution unit in the unscrambled form. The unscrambled data and the scrambled data may have the same set of bits arranged in different orders.

公开(公告)号：US20250165256A1

公开(公告)日：2025-05-22

申请号：US19023081

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: A computing device (e.g., a processor) having a plurality of branch target buffers. A first branch target buffer in the plurality of branch target buffers is used in execution of a set of instructions containing a call to a subroutine. In response to the call to the subroutine, a second branch target buffer is allocated from the plurality of branch target buffers for execution of instructions in the subroutine. The second branch target buffer is cleared before the execution of the instructions in the subroutine. The execution of the instructions in the subroutine is restricted to access the second branch target buffer and blocked from accessing branch target buffers other than the second branch target buffer.