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公开(公告)号：US12075042B2
公开(公告)日：2024-08-27
申请号：US18208380
申请日：2023-06-12
Inventor： Chong Soon Lim , Hai Wei Sun , Jing Ya Li , Han Boon Teo , Che-Wei Kuo , Chu Tong Wang , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Yusuke Kato
IPC: H04N19/117 , H04N19/132 , H04N19/169 , H04N19/82
CPC classification number: H04N19/117 , H04N19/132 , H04N19/188 , H04N19/82
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes information for deriving a parameter into a header of a bitstream; filters reconstructed samples in a first image using a filtering process, to generate a second image; determines whether the parameter has a predefined value; encodes a third image using the second image when the parameter has the predefined value; and encodes the third image using the first image when the parameter does not have the predefined value.
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公开(公告)号：US12069245B2
公开(公告)日：2024-08-20
申请号：US17945629
申请日：2022-09-15
Inventor： Ru Ling Liao , Chong Soon Lim , Hai Wei Sun , Han Boon Teo , Jing Ya Li , Sughosh Pavan Shashidhar , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/105 , H04N19/159 , H04N19/176 , H04N19/46
CPC classification number: H04N19/105 , H04N19/159 , H04N19/176 , H04N19/46
Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.
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公开(公告)号：US20240259595A1
公开(公告)日：2024-08-01
申请号：US18626825
申请日：2024-04-04
Inventor： Chong Soon LIM , Zheng Wu , Han Boon Teo , Keng Liang Loi , Chung Dean Han , Georges Nader , Farman Dumanov , Toshiyasu Sugio , Noritaka Iguchi , Takahiro Nishi
IPC: H04N19/597 , G06T17/20
CPC classification number: H04N19/597 , G06T17/20
Abstract: An encoding device including memory and a circuit. In operation, the circuit: encodes first vertex information, second vertex information, and third vertex information, the first vertex information indicating a position of a first vertex of a first triangle that is a triangle in a three-dimensional mesh and on a first plane, the second vertex information indicating a position of a second vertex of the first triangle, the third vertex information indicating a position of a third vertex of the first triangle; and encodes, as fourth vertex information indicating a position of a fourth vertex of a second triangle, (i) dihedral angle information indicating a dihedral angle formed by the first plane and a second plane and (ii) identifying information for identifying a position of a fifth vertex that is a virtual vertex of a third triangle.
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公开(公告)号：US11895322B2
公开(公告)日：2024-02-06
申请号：US18056963
申请日：2022-11-18
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N11/02 , H04N19/52 , H04N19/119 , H04N19/176
CPC classification number: H04N19/52 , H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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公开(公告)号：US11889105B2
公开(公告)日：2024-01-30
申请号：US18057440
申请日：2022-11-21
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N11/02 , H04N19/52 , H04N19/119 , H04N19/176
CPC classification number: H04N19/52 , H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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Patent Agency Ranking
公开(公告)号：US11882283B2
公开(公告)日：2024-01-23
申请号：US18148990
申请日：2022-12-30
Inventor： Sughosh Pavan Shashidhar , Hai Wei Sun , Chong Soon Lim , Ru Ling Liao , Han Boon Teo , Jing Ya Li , Takahiro Nishi , Kiyofumi Abe , Ryuichi Kanoh , Tadamasa Toma
IPC: H04N11/02 , H04N19/119 , H04N19/176 , H04N19/184 , H04N19/60
CPC classification number: H04N19/119 , H04N19/176 , H04N19/184 , H04N19/60
Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; splits the block into a plurality of sub blocks in a second direction parallel to the second shorter side of the block when the ternary split process is not allowed; and encodes the plurality of sub blocks.
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公开(公告)号：US11876992B2
公开(公告)日：2024-01-16
申请号：US17743348
申请日：2022-05-12
Inventor： Chong Soon Lim , Hai Wei Sun , Sughosh Pavan Shashidhar , Ru Ling Liao , Han Boon Teo , Takahiro Nishi , Ryuichi Kanoh , Tadamasa Toma
IPC: H04N19/44 , H04N19/119 , H04N19/124 , H04N19/13 , H04N19/159 , H04N19/176
CPC classification number: H04N19/44 , H04N19/119 , H04N19/124 , H04N19/13 , H04N19/159 , H04N19/176
Abstract: An image decoder parses an encoded bitstream to obtain a first parameter and a second parameter, and derives a partition mode based on the first and second parameters. Responsive to the derived partition mode being a first partition mode, the image decoder executes the first partition mode including; splitting a block of a picture into a plurality of first blocks including a N×2N block sized N pixels by 2N pixels; splitting the N×2N block, wherein a ternary split is allowed to split the N×2N block in a vertical direction, which is a direction along the 2N pixels, into a plurality of sub blocks including at least one sub block sized N/4×2N, while a binary split is not allowed to split the N×2N block in the vertical direction into two sub blocks that are equally sized N/2×2N; and decoding the plurality of sub blocks.
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公开(公告)号：US11849147B2
公开(公告)日：2023-12-19
申请号：US17725084
申请日：2022-04-20
Inventor： Jing Ya Li , Che Wei Kuo , Chong Soon Lim , Chu Tong Wang , Han Boon Teo , Hai Wei Sun , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Yusuke Kato
IPC: H04N19/66 , H04N19/122 , H04N19/176 , H04N19/103 , H04N19/96
CPC classification number: H04N19/66 , H04N19/122 , H04N19/176 , H04N19/103 , H04N19/96
Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.
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公开(公告)号：US11825126B2
公开(公告)日：2023-11-21
申请号：US17507571
申请日：2021-10-21
Inventor： Jing Ya Li , Han Boon Teo , Chong Soon Lim , Hai Wei Sun , Che-Wei Kuo , Chu Tong Wang , Tadamasa Toma , Takahiro Nishi , Kiyofumi Abe , Yusuke Kato
IPC: H04N19/82 , H04N19/107 , H04N19/176 , H04N19/186
CPC classification number: H04N19/82 , H04N19/107 , H04N19/176 , H04N19/186
Abstract: A decoder includes memory and a processor coupled to the memory and configured to: generate a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component; clip the first coefficient value such that the clipped first coefficient value is within a first range from −27 to 27−1; generate a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component; clip the second coefficient value such that the clipped second coefficient value is within a second range different from the first range; generate a third coefficient value by adding the clipped first coefficient value to the clipped second coefficient value; and generate a third reconstructed image sample of the chroma component using the third coefficient value.
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公开(公告)号：US11805273B2
公开(公告)日：2023-10-31
申请号：US17886281
申请日：2022-08-11
Inventor： Jing Ya Li , Chong Soon Lim , Sughosh Pavan Shashidhar , Ru Ling Liao , Hai Wei Sun , Han Boon Teo , Kiyofumi Abe , Tadamasa Toma , Takahiro Nishi
IPC: H04N19/00 , H04N19/513 , H04N19/119 , H04N19/176 , H04N19/96
CPC classification number: H04N19/521 , H04N19/119 , H04N19/176 , H04N19/96
Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry corrects a base motion vector using a correction value in a fixed direction; and encodes a current partition by using the corrected base motion vector corrected. The correction value is specified by an index indicating one of correction values included in a table. The table is selected from among a plurality of tables, wherein the correction values in one of the plurality of tables have different increments from the correction values in another one of the plurality of tables.
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