公开(公告)号：US06735684B1

公开(公告)日：2004-05-11

申请号：US09661051

申请日：2000-09-13

申请人： Satoshi Shigematsu ,  Hiroki Morimura ,  Katsuyuki Machida

发明人： Satoshi Shigematsu ,  Hiroki Morimura ,  Katsuyuki Machida

IPC分类号： G06F1580

CPC分类号： G06K9/00006 ,  G06F15/8007 ,  G06K9/00986

摘要： A parallel-processing apparatus includes a plurality of cells, variable-delay circuits, a signal output unit, a delay counter, and an accumulation unit. Each cell has a processing circuit for performing arbitrary processing. The variable-delay circuits change the signal propagation delay in accordance with the processing results of the processing circuits. The signal output unit outputs a measurement input signal to the first variable-delay circuit of a variable-delay circuit array. The delay counter receives the measurement input signal output form the signal output unit and a measurement output signal output from the variable-delay circuit array, and obtains the signal propagation delay time of the variable-delay circuit array upon the basis of the measurement input and output signals. The accumulation unit accumulates the processing results of the processing circuits. A parallel processing method is also disclosed.

摘要翻译： 并行处理装置包括多个单元，可变延迟电路，信号输出单元，延迟计数器和累积单元。 每个单元具有用于执行任意处理的处理电路。 可变延迟电路根据处理电路的处理结果改变信号传播延迟。 信号输出单元向可变延迟电路阵列的第一可变延迟电路输出测量输入信号。 延迟计数器接收从信号输出单元输出的测量输入信号和从可变延迟电路阵列输出的测量输出信号，并根据测量输入获得可变延迟电路阵列的信号传播延迟时间， 输出信号。 累加单元积累处理电路的处理结果。 还公开了并行处理方法。

公开(公告)号：US06438257B1

公开(公告)日：2002-08-20

申请号：US09347240

申请日：1999-07-02

申请人： Hiroki Morimura ,  Satoshi Shigematsu ,  Katsuyuki Machida ,  Akihiko Hirata

发明人： Hiroki Morimura ,  Satoshi Shigematsu ,  Katsuyuki Machida ,  Akihiko Hirata

IPC分类号： G06K900

CPC分类号： G01R27/2605 ,  G06K9/0002 ,  G11C11/24 ,  G11C27/028

摘要： A small capacitance change detection device includes a capacitance detection element, signal generation circuit, signal amplification circuit, and output circuit. The signal amplification circuit includes a first transistor and first to third voltage sources. The second or third voltage source is connected to the other output terminal of the first transistor via a first switch. A voltage to be applied from the second voltage source to the other output terminal is set to have a value equal to or larger than a value obtained by subtracting a threshold voltage of the first transistor from a voltage of the first voltage source while a voltage to be applied from the third voltage source to the other output terminal is set to have a value equal to or smaller than a value obtained by subtracting the threshold voltage from the voltage of the first voltage source. The output circuit is connected to a connection point between the other output terminal of the first transistor and the first switch and, after a voltage of the second or third voltage source is applied to the connection point in an ON state of the first switch, receives the voltage at the connection point on the basis of an OFF state of the first switch and charge control by the signal generation circuit after the first switch is turned off.

摘要翻译： 小电容变化检测装置包括电容检测元件，信号生成电路，信号放大电路和输出电路。 信号放大电路包括第一晶体管和第一至第三电压源。 第二或第三电压源通过第一开关连接到第一晶体管的另一个输出端。 将从第二电压源施加到另一输出端子的电压设定为等于或大于从第一电压源的电压减去第一晶体管的阈值电压而获得的值，同时将电压 从第三电压源施加到另一输出端子的值设定为等于或小于从第一电压源的电压减去阈值电压获得的值。 输出电路连接到第一晶体管的另一输出端和第一开关之间的连接点，并且在第二或第三电压源的电压施加到第一开关的接通状态的连接点之后，接收 基于第一开关的OFF状态的连接点处的电压和在第一开关之后的信号发生电路的充电控制被断开。

公开(公告)号：US6060756A

公开(公告)日：2000-05-09

申请号：US263678

申请日：1999-03-05

申请人： Katsuyuki Machida ,  Satoshi Shigematsu ,  Hiroki Morimura ,  Akihiko Hirata

发明人： Katsuyuki Machida ,  Satoshi Shigematsu ,  Hiroki Morimura ,  Akihiko Hirata

IPC分类号： G01B7/004 ,  G01B7/34 ,  G06K9/00 ,  H01L29/82 ,  H01L31/0203 ,  H01L31/0232

CPC分类号： G06K9/0002 ,  G01B7/004 ,  G01B7/34

摘要： A surface shape recognition sensor of this invention includes at least a plurality of capacitance detection elements having sensor electrodes arranged in the same plane on an interlevel dielectric film formed on a semiconductor substrate to be insulated/isolated from each other, capacitance detection means for detecting the capacitances of the capacitance detection elements, and a stationary electrode disposed on the interlevel dielectric film to be insulated/isolated from the sensor electrodes. When an object to be recognized touches the upper surface of the stationary electrode, the capacitances detected by the capacitance detection elements change in accordance with the recesses/projections on the upper surface.

摘要翻译： 本发明的表面形状识别传感器至少包括多个电容检测元件，该电容检测元件具有布置在形成于半导体衬底上的层间电介质膜上的同一平面内的绝缘/隔离的电容检测元件，用于检测 电容检测元件的电容和设置在层间电介质膜上的与传感器电极绝缘/隔离的固定电极。 当待识别的物体接触固定电极的上表面时，由电容检测元件检测的电容根据上表面上的凹凸来改变。