公开(公告)号：US07292065B2

公开(公告)日：2007-11-06

申请号：US10910891

申请日：2004-08-03

申请人： Henry Y. Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Tri Hoang

发明人： Henry Y. Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Tri Hoang

IPC分类号： H03K19/173

CPC分类号： H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.

摘要翻译： 提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。 在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。 此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。