公开(公告)号：US11973501B2

公开(公告)日：2024-04-30

申请号：US17730352

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： H03K19/1776 ,  H03K19/17736 ,  H03K19/17784

CPC分类号： H03K19/1776 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17784

摘要： A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US20240113715A1

公开(公告)日：2024-04-04

申请号：US17956912

申请日：2022-09-30

申请人： Crossbar, Inc.

发明人： Sung Hyun Jo

IPC分类号： H03K19/17768 ,  H03K19/0175 ,  H03K19/17784

CPC分类号： H03K19/17768 ,  H03K19/017545 ,  H03K19/17784

摘要： A physical unclonable function (PUF) can be implemented on a transistor of an integrated circuit device to generate PUF data. A potential difference is supplied across a gate insulator to induce a conductive breakdown in the gate insulator material. Location of the conductive breakdown within the gate insulator and in relation to the source node and drain node can be highly unpredictable, randomly resulting in a higher gate-source current or higher gate-drain current, respectively. The gate-source or gate-drain current can be measured and digitized to generate the PUF data value from the transistor. Moreover, PUF data values generated from multiple transistors can be highly non-correlated and useful for a random data sequence for cryptographic applications and other security applications.

公开(公告)号：US11935616B2

公开(公告)日：2024-03-19

申请号：US17669565

申请日：2022-02-11

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kangling Ji

IPC分类号： G11C7/00 ,  G11C7/10 ,  H03K19/0175 ,  H03K19/17784 ,  H03K19/20

CPC分类号： G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  H03K19/017509 ,  H03K19/17784 ,  H03K19/20

摘要： Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common circuit, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical circuit, connected to the common circuit, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical circuit, connected to the common circuit, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal.

公开(公告)号：US11863184B1

公开(公告)日：2024-01-02

申请号：US17648114

申请日：2022-01-14

申请人： Kepler Computing Inc.

发明人： Amrita Mathuriya ,  Nabil Imam ,  Ikenna Odinaka ,  Rafael Rios ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H03K19/23 ,  H03K19/17784 ,  H03K19/185 ,  H03K19/17736

CPC分类号： H03K19/23 ,  H03K19/17744 ,  H03K19/17784 ,  H03K19/185

摘要： Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

公开(公告)号：US11848670B2

公开(公告)日：2023-12-19

申请号：US17659423

申请日：2022-04-15

申请人： Xilinx, Inc.

发明人： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC分类号： H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC分类号： H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

摘要： An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

公开(公告)号：US20230396463A1

公开(公告)日：2023-12-07

申请号：US18236477

申请日：2023-08-22

申请人： SEW-EURODRIVE GMBH & CO. KG

发明人： Hans Jürgen KOLLAR

IPC分类号： H04L12/40 ,  H03K19/17784

CPC分类号： H04L12/40013 ,  H03K19/17784 ,  H04L12/40039 ,  H04L2012/40215

摘要： In a system and method of operating a system that includes a controller and a first bus participant and a successor, the bus participant and successor each has a circuit arrangement arranged between an output and an input, a first resistor is arranged between the output and the supply voltage terminal, a second resistor is arranged between the input and a ground terminal, a third resistor can be arranged between the input and the supply voltage terminal by a first controllable semiconductor switch, and a fourth resistor can be arranged between the output and the supply voltage terminal by a second controllable semiconductor switch.

公开(公告)号：US11831321B2

公开(公告)日：2023-11-28

申请号：US17772482

申请日：2021-06-08

申请人： BOE Technology Group Co., Ltd.

发明人： Aixiang Qi ,  Xiangye Wei ,  Yiming Bai ,  Jie Feng ,  Shuai Wang ,  Kening Zhao

IPC分类号： H03L7/083 ,  H03K3/017 ,  H03K19/17784 ,  H03L7/099

CPC分类号： H03L7/083 ,  H03K3/017 ,  H03K19/17784 ,  H03L7/0995

摘要： Provided is a clock signal generation circuit. The clock signal generation circuit includes a control word generation circuit, an initial clock generation circuit and a spread spectrum clock generation circuit, wherein the control word generation circuit is connected to the initial clock generation circuit and the spread spectrum clock generation circuit; the initial clock generation circuit is further connected to the spread spectrum clock generation circuit.

公开(公告)号：US11811402B1

公开(公告)日：2023-11-07

申请号：US17648114

申请日：2022-01-14

申请人： Kepler Computing Inc.

发明人： Amrita Mathuriya ,  Nabil Imam ,  Ikenna Odinaka ,  Rafael Rios ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H03K19/23 ,  H03K19/17784 ,  H03K19/185 ,  H03K19/17736

CPC分类号： H03K19/23 ,  H03K19/17744 ,  H03K19/17784 ,  H03K19/185

摘要： Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

公开(公告)号：US20230353155A1

公开(公告)日：2023-11-02

申请号：US17730352

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17736

CPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17744 ,  H03K19/1774

摘要： A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US11757451B2

公开(公告)日：2023-09-12

申请号：US17652905

申请日：2022-02-28

申请人： Everspin Technologies, Inc.

发明人： Dimitri Houssameddine ,  Syed M. Alam ,  Sanjeev Aggarwal

IPC分类号： H03K19/1776 ,  G11C11/16 ,  G11C13/00 ,  H03K19/17784 ,  H03K19/17724 ,  G06F21/78

CPC分类号： H03K19/1776 ,  G11C11/1675 ,  G11C13/0069 ,  H03K19/17724 ,  H03K19/17784 ,  G06F21/78

摘要： The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.