公开(公告)号：US5856214A

公开(公告)日：1999-01-05

申请号：US610475

申请日：1996-03-04

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L21/38 ,  H01L21/385 ,  H01L23/60

CPC分类号： H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  Y10S148/174 ,  Y10S438/983

摘要： The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. The zener diode is composed of a p-type doped region and an n-type doped region, wherein one of the doped regions, formed by deep diffusing impurities from a doped polysilicon layer, is arranged between two adjacent well regions. During an ESD event, the zener diode incurs breakdown to lower the trigger voltage of the lateral SCR device to within a range of about 5-7 Volts to thereby discharge the ESD current prior to damage of an internal circuit being protected.

摘要翻译： 根据本发明的方法与常规CMOS制造工艺兼容以形成在半导体衬底中构成片上ESD保护电路的齐纳二极管和横向可控硅整流器。 齐纳二极管由p型掺杂区域和n型掺杂区域组成，其中通过深度扩散来自掺杂多晶硅层的杂质形成的掺杂区域之一布置在两个相邻的阱区域之间。 在ESD事件期间，齐纳二极管引起击穿以将横向SCR器件的触发电压降低到约5-7伏的范围内，从而在被保护的内部电路损坏之前放电ESD电流。

公开(公告)号：US5767537A

公开(公告)日：1998-06-16

申请号：US753281

申请日：1996-11-22

申请人： Ta-Lee Yu ,  Konrad Kwang-Leei Young

发明人： Ta-Lee Yu ,  Konrad Kwang-Leei Young

IPC分类号： H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0262 ,  Y10S388/919

摘要： An SCR circuit formed on a semiconductor substrate includes a well region, a first diffusion region and a second diffusion region in the well region, and a third diffusion region in the substrate. The SCR circuit also includes a capacitor connected between the first diffusion region and the third diffusion region. The junction region between the well region and the diffusion region is forward biased when an electrostatic force is applied to the SCR circuit, thereby triggering the SCR circuit to discharge the electrostatic force.

摘要翻译： 形成在半导体衬底上的SCR电路包括阱区中的阱区，第一扩散区和第二扩散区，以及衬底中的第三扩散区。 SCR电路还包括连接在第一扩散区和第三扩散区之间的电容器。 当静电力施加到SCR电路时，阱区域和扩散区域之间的接合区域被正向偏置，从而触发SCR电路以释放静电力。

公开(公告)号：US5715127A

公开(公告)日：1998-02-03

申请号：US642194

申请日：1996-05-06

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L23/60 ,  H01L27/02 ,  H02H3/22

CPC分类号： H01L23/60 ,  H01L27/0248 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107

摘要： An integrated circuit package includes a semiconductor chip, bonding pads on the semiconductor chip, a metal lead frame contacting electrically with the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin. The non-wired pin is wire-bonded to the metal lead frame to prevent electrostatic discharge failure of the integrated circuit package due to electrostatic discharge stressing of the non-wired pin.

摘要翻译： 集成电路封装包括半导体芯片，半导体芯片上的接合焊盘，与半导体芯片电接触的金属引线框架，分别连接到接合焊盘的多个有线引脚和至少一个非有线引脚。 非接线引脚与金属引线框线接合，防止集成电路封装由于非接线引脚的静电放电而产生静电放电故障。

公开(公告)号：US5631793A

公开(公告)日：1997-05-20

申请号：US523653

申请日：1995-09-05

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Tao Cheng ,  Chau-Neng Wu ,  Ta-Lee Yu

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Tao Cheng ,  Chau-Neng Wu ,  Ta-Lee Yu

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.

摘要翻译： 本发明涉及用于保护IC的内部电路和/或输出缓冲器免受ESD电流损坏的电容器对偶静电放电（ESD）保护电路。 根据本发明的电容耦合ESD保护电路包括用于旁路ESD电流的ESD旁路装置，用于将一部分电压耦合到ESD旁路装置的电容器耦合电路和用于保持ESD电压的电位调节装置 在低电位电平下为内部电路传输。 通过使用本ESD保护电路，可以降低回跳击穿电压，以保护内部电路的非常薄的栅极氧化物，特别是在亚微米CMOS技术中。