公开(公告)号：US20240258999A1

公开(公告)日：2024-08-01

申请号：US18103753

申请日：2023-01-31

Applicant: Texas Instruments Incorporated

Inventor： Orlando Lazaro ,  Henry Litzmann Edwards ,  Andres Arturo Blanco ,  Kushal D. Murthy ,  Ankur Chauhan

IPC: H03K3/011 ,  H01L27/02 ,  H03K17/687

CPC classification number: H03K3/011 ,  H01L27/0251 ,  H03K17/687

Abstract: The present disclosure introduces integrated circuits and related manufacturing methods, wherein each integrated circuit includes an electronic device and a thermoelectric circuit. The electronic device is formed in and/or over a semiconductor substrate. The thermoelectric circuit includes thermopiles formed in and/or over the semiconductor substrate and electrically connected in series. The thermoelectric circuit is configured to modulate operation of the electronic device in response to a potential produced by the plurality of thermopiles.

公开(公告)号：US11996444B2

公开(公告)日：2024-05-28

申请号：US17844344

申请日：2022-06-20

Applicant: MagnaChip Semiconductor, Ltd.

Inventor： Guk Hwan Kim

IPC: H01L29/06 ,  H01L27/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/0638 ,  H01L27/0251 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42364

Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.

公开(公告)号：US11955544B2

公开(公告)日：2024-04-09

申请号：US17454433

申请日：2021-11-10

Applicant: ROHM CO., LTD.

Inventor： Kentaro Nasu

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/866

CPC classification number: H01L29/7808 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

公开(公告)号：US11955473B2

公开(公告)日：2024-04-09

申请号：US17838477

申请日：2022-06-13

Applicant: 138 East LCD Advancements Limited

Inventor： Yutaka Kobashi

IPC: H01L27/02 ,  G02F1/1362 ,  G09G3/3208 ,  G09G3/3225 ,  G09G3/36 ,  H01L27/12

CPC classification number: H01L27/0251 ,  G02F1/136204 ,  G09G3/3208 ,  G09G3/3225 ,  G09G3/36 ,  G09G3/3648 ,  H01L27/1214 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2330/04 ,  H01L27/12

Abstract: To prevent an electrostatic damage on a display device formed with a driving circuit. Protective circuits are provided not only at input terminal parts, but also at intermediate parts of a circuit or at the ends of wiring lines. Otherwise, the protective circuits are provided at the ends of the wiring lines and at the places immediately before and after the input terminals, respectively, and then the circuit is interposed therebetween. Further, the protective circuits are provided around a circuit with a large current consumption.

公开(公告)号：US20230326801A1

公开(公告)日：2023-10-12

申请号：US18335154

申请日：2023-06-15

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/02 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/423

CPC classification number: H01L21/823425 ,  H01L29/0607 ,  H01L27/0251 ,  H01L29/4925 ,  H01L29/7832 ,  H01L21/8249 ,  H01L29/7835 ,  H01L21/823437 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/78

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US11735521B2

公开(公告)日：2023-08-22

申请号：US17510190

申请日：2021-10-25

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Sarvesh H. Kulkarni ,  Vincent E. Dorgan ,  Uddalak Bhattacharya

IPC: H10B20/20 ,  H01L23/525 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L23/5252 ,  H01L27/0251 ,  H01L29/7833 ,  H10B20/20

Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

公开(公告)号：US11695413B2

公开(公告)日：2023-07-04

申请号：US17508176

申请日：2021-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

Inventor： Lei Pan ,  Yaqi Ma ,  Jing Ding ,  Zhang-Ying Yan

IPC: H01L27/02 ,  H03K17/687

CPC classification number: H03K17/6872 ,  H01L27/0251 ,  H01L27/0274

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

公开(公告)号：US20230207554A1

公开(公告)日：2023-06-29

申请号：US17564157

申请日：2021-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peter Mueller ,  Thomas Morf ,  Mridula Prathapan ,  Matthias Mergenthaler

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/872 ,  G06N10/00

CPC classification number: H01L27/0251 ,  G06N10/00 ,  H01L29/872 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

公开(公告)号：US20230200188A1

公开(公告)日：2023-06-22

申请号：US17922406

申请日：2021-03-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dengyun CHEN ,  Yunjin LIU ,  Xueyan TIAN

IPC: H10K59/80 ,  H10K59/131 ,  H01L27/02

CPC classification number: H10K59/873 ,  H10K59/131 ,  H10K59/878 ,  H01L27/0251

Abstract: Embodiments of the present disclosure provide a display panel and a display device, the display panel includes: a base substrate; a plurality of light emitting devices on the base substrate; an encapsulation layer covering the light emitting devices; a mirror layer located on a side of the encapsulation layer away from the base substrate, the mirror layer including a plurality of first openings, and an orthographic projection of each first opening on the base substrate overlapping an orthographic projection of at least one light emitting device on the base substrate; a transparent filling layer located on a side of the encapsulation layer away from the base substrate, at least part of the transparent filling layer being located in the first openings.

公开(公告)号：US20230163173A1

公开(公告)日：2023-05-25

申请号：US17910932

申请日：2021-03-18

Applicant: Elmos Semiconductor SE ,  Hyundai Mobis Co., Ltd.

Inventor： Fikret Abaza ,  Andre Sudhaus ,  Uwe Friemann ,  Andreas Friesen ,  Mats Schmalhorst ,  Marco Liedtke

IPC: H01L29/12 ,  B60R21/01 ,  H01L21/8249

CPC classification number: H01L29/12 ,  B60R21/01 ,  H01L21/8249 ,  B60R2021/01272 ,  B60R2021/01211 ,  H01L27/0251

Abstract: Devices and methods prevent injection of a substrate current into the substrate Sub of a CMOS circuit. The devices detect the potential of a contact of the integrated CMOS circuit, compare the value of the potential detected with a reference value and connect the contact to a leakage circuit node for discharging the current such that same does not flow to ground via the parasitic bipolar lateral structure. The leakage circuit node can be connected to the reference potential line or to another line that has a higher potential than the reference potential line. This electrical connection is activated when the value of the potential of the contact is lower than or equal to a reference value.