公开(公告)号：US07065141B2

公开(公告)日：2006-06-20

申请号：US10156557

申请日：2002-05-24

申请人： Shigeyuki Okada

发明人： Shigeyuki Okada

IPC分类号： H04B1/66 ,  H04N11/02 ,  H04N11/04 ,  H04N7/12

CPC分类号： H04N5/783 ,  H04N9/8042

摘要： When a reverse reproduction is instructed, an MPEG video stream is once decoded and is converted to image video signals by a first display circuit. Thereafter, the image video signals are again recoded by an image input circuit and an MPEG video encoder, so as to be overwritten in a storage area of a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series manner and decodes it successively. Then the thus decoded data are converted to image video signals by a second display circuit, so as to be displayed on a display.

公开(公告)号：US5748514A

公开(公告)日：1998-05-05

申请号：US564480

申请日：1995-11-29

申请人： Shigeyuki Okada ,  Naoki Tanahashi ,  Hayato Nakashima

发明人： Shigeyuki Okada ,  Naoki Tanahashi ,  Hayato Nakashima

IPC分类号： H04N19/60 ,  G06F17/14 ,  G06T9/00 ,  H04N1/41 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/625 ,  H04N19/85 ,  H04N19/91

CPC分类号： G06F17/147 ,  G06T9/007

摘要： Discrete cosine transform circuits suitable for inverse discrete cosine transform (IDCT) or forward discrete cosine transform (FDCT) are disclosed. An IDCT circuit includes a group of multipliers and a group of adders/subtracters. The multipliers receive plural pieces of input data which are externally supplied in parallel. Each multiplier has a cosine constant to multiply to the received input data. The adders/subtracters receive multiplication results from the multipliers and perform addition/subtraction thereon to produce output data, which is the result of inverse discrete cosine transform of the input data. An FDCT circuit includes a group of input-stage adders/subtracters, a group of multipliers, and a group of output-stage adders. The input-stage adders/subtracters perform addition/subtraction on input data which are externally supplied in parallel. Computation results of the input-stage adders/subtracters is supplied to the multipliers. The output-stage adders receive multiplication results from the multipliers and produce output data, which is the result of forward discrete cosine transform of the input data. The discrete cosine transform circuits are particularly suitable for use in MPEG video encoders/decoders.

摘要翻译： 公开了适用于逆离散余弦变换（IDCT）或前向离散余弦变换（FDCT）的离散余弦变换电路。 IDCT电路包括一组乘法器和一组加法器/减法器。 乘法器接收外部并行提供的多个输入数据。 每个乘法器具有乘法常数以乘以接收到的输入数据。 加法器/减法器从乘法器接收乘法结果，并在其上执行加法/减法以产生输出数据，这是输入数据的反离散余弦变换的结果。 FDCT电路包括一组输入级加法器/减法器，一组乘法器和一组输出级加法器。 输入级加法器/减法器对外部并行提供的输入数据执行加法/减法。 输入级加法器/减法器的计算结果提供给乘法器。 输出级加法器从乘法器接收乘法结果并产生输出数据，这是输入数据的前向离散余弦变换的结果。 离散余弦变换电路特别适用于MPEG视频编码器/解码器。