公开(公告)号：US20130187227A1

公开(公告)日：2013-07-25

申请号：US13746150

申请日：2013-01-21

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7836 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.

公开(公告)号：US20130149829A1

公开(公告)日：2013-06-13

申请号：US13689433

申请日：2012-11-29

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L29/66

CPC classification number: H01L28/20 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66181 ,  H01L29/66477 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7847 ,  H01L29/94

Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.

Abstract translation: 在本发明的实施例中，公开了形成NMOS（n型金属氧化物半导体）晶体管的方法。 双掩模图案用于离子注入NMOS晶体管的源极/漏极区域。 第一个掩模允许第一剂量的As（砷），P（磷）和N（氮）离子注入。 在这些剂量被离子注入之后，进行高温（900-1050℃）尖峰退火以激活形成的源/排水沟。 第二掩模允许在源极/漏极区域中注入第二剂量的磷。 磷的第二剂量通常高于第一剂量的磷。 磷的第二剂量降低了Rsd（源区和漏区的电阻）和掺杂n型多晶硅块。