公开(公告)号：US08519467B2

公开(公告)日：2013-08-27

申请号：US13051516

申请日：2011-03-18

申请人： Masato Endo ,  Mitsuhiro Noguchi

发明人： Masato Endo ,  Mitsuhiro Noguchi

IPC分类号： H01L27/06

CPC分类号： H01L27/105 ,  H01L27/0629 ,  H01L27/11531 ,  H01L28/20

摘要： According to one embodiment, a semiconductor device includes a first resistance element including a first conductive material, an inter-gate insulation film formed on both ends of the first conductive material in a first direction, and a second conductive material formed above the first conductive material and configured to connect with the first conductive material via a first connection region from which the inter-gate insulation film is removed, and a second resistance element including a third conductive material, the inter-gate insulation film formed on both ends of the third conductive material in the first direction, and a fourth conductive material formed above the third conductive material and configured to connect with the third conductive material via a second connection region from which the inter-gate insulation film is removed, wherein a length of the second connection region is greater than a length of the first connection region in the first direction.

摘要翻译： 根据一个实施例，半导体器件包括第一电阻元件，第一电阻元件包括第一导电材料，在第一方向上形成在第一导电材料的两端上的栅极间绝缘膜和形成在第一导电材料上方的第二导电材料 并且被配置为经由去除所述栅极间绝缘膜的第一连接区域与所述第一导电材料连接，以及包括第三导电材料的第二电阻元件，所述栅极间绝缘膜形成在所述第三导电 材料在第一方向上形成，第四导电材料形成在第三导电材料之上，并被配置为经由去除栅间绝缘膜的第二连接区域与第三导电材料连接，其中第二连接区域 大于第一方向上的第一连接区域的长度。

公开(公告)号：US08377720B2

公开(公告)日：2013-02-19

申请号：US11419079

申请日：2006-05-18

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroyuki Nitta

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroyuki Nitta

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed.

摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成不同厚度的栅极绝缘膜的工艺，沉积构成栅电极的膜，去除在包括晶体管的晶体管的杂质扩散区域表面上形成的具有不同厚度的栅极绝缘膜 栅极电极和将杂质掺杂到去除栅极绝缘膜的部分中。

公开(公告)号：US08319316B2

公开(公告)日：2012-11-27

申请号：US12788784

申请日：2010-05-27

申请人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Yoshiko Kato ,  Mitsuhiro Noguchi ,  Masato Endo

发明人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Yoshiko Kato ,  Mitsuhiro Noguchi ,  Masato Endo

IPC分类号： H01L21/02

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/41775 ,  H01L29/7838

摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

摘要翻译： 半导体存储器件包括第一晶体管。 第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。 沟道区具有第一杂质浓度。 源区和漏区具有第二杂质浓度。 重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。 接触区域具有第四杂质浓度。 杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。 杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

公开(公告)号：US08288751B2

公开(公告)日：2012-10-16

申请号：US12759107

申请日：2010-04-13

申请人： Mitsuhiko Noda ,  Mitsuhiro Noguchi ,  Hiroomi Nakajima ,  Masato Endo

发明人： Mitsuhiko Noda ,  Mitsuhiro Noguchi ,  Hiroomi Nakajima ,  Masato Endo

IPC分类号： H01L27/11

CPC分类号： H01L27/105 ,  H01L27/1021 ,  H01L27/1052 ,  H01L27/24

摘要： A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.

摘要翻译： 半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括多个存储器单元，多个存储单元阵列堆叠在半导体衬底上以形成三维结构，第一阱形成在半导体衬底中并具有 第一导电类型，元件隔离绝缘膜，其包括比第一阱中的第一阱的底表面浅的底表面，并且埋在半导体衬底中，第二阱包括比第一阱的底表面浅的底表面 在第一阱中沿着元件隔离绝缘膜的至少一部分的底表面形成并由具有第二导电类型的杂质和与第一阱电连接的接触线形成。

公开(公告)号：US08183552B2

公开(公告)日：2012-05-22

申请号：US12540896

申请日：2009-08-13

申请人： Shingo Nakajima ,  Eiji Ito ,  Mitsuhiro Noguchi

发明人： Shingo Nakajima ,  Eiji Ito ,  Mitsuhiro Noguchi

IPC分类号： H01L29/02

CPC分类号： H01L27/24

摘要： A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.

摘要翻译： 一种具有设置在第一绝缘体上并沿第一方向延伸的第一布线层的半导体存储器件和在第一布线层上以柱形形式设置的非易失性存储单元， 元件和可变电阻元件串联连接。 可变电阻元件的电阻值根据施加到其上的电压或电流而变化。 阻挡层设置在存储单元上并且被配置在面内方向上。 导电层设置在阻挡层上并且被配置在面内方向上。 第二绝缘体设置在第一绝缘体上并且覆盖存储单元，阻挡层和导电层的侧表面。 第二布线层设置在导电层上并沿第二方向延伸。

公开(公告)号：US08159019B2

公开(公告)日：2012-04-17

申请号：US12338417

申请日：2008-12-18

申请人： Yoshiko Kato ,  Mitsuhiro Noguchi

发明人： Yoshiko Kato ,  Mitsuhiro Noguchi

IPC分类号： H01L29/72

CPC分类号： H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.

摘要翻译： 半导体存储器件包括第一有源区，第二有源区，第一元件隔离区和第二元件隔离区。 第一有源区形成在半导体衬底中。 第二有源区形成在半导体衬底中。 第一元件隔离区域使彼此相邻的第一有源区域电隔离。 第二元件隔离区域将彼此相邻的第二有源区域电隔离。 与第二元件隔离区域的侧面接触的第二有源区域的一部分中的杂质浓度高于第二有源区域的中心部分的杂质浓度，第一有源区域的一部分中的杂质浓度在 与第一元件隔离区域的侧面的接触与第一有源区域中的相同。

公开(公告)号：US20120020158A1

公开(公告)日：2012-01-26

申请号：US13187000

申请日：2011-07-20

申请人： Tohru OZAKI ,  Mitsuhiro Noguchi ,  Hideaki Maekawa ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Kazuhito Kobayashi ,  Hidefumi Mukai ,  Hiroyuki Nitta

发明人： Tohru OZAKI ,  Mitsuhiro Noguchi ,  Hideaki Maekawa ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Kazuhito Kobayashi ,  Hidefumi Mukai ,  Hiroyuki Nitta

IPC分类号： G11C16/04 ,  H01L21/78

CPC分类号： H01L27/11521

摘要： A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).

摘要翻译： 存储单元阵列包括沿第一方向布置的存储器串。 字线和选择栅极线在垂直于第一方向的第二方向上延伸。 选择栅极线也沿第二方向延伸。 字线在第一方向上具有第一线宽度并且以它们之间的第一距离布置。 选择栅极线包括在第一方向上的第一互连，第一互连具有大于第一线宽的第二线宽，以及从第一互连的端部延伸的第二互连，第二互连具有第三线宽 与第一行宽度相同。 与选择栅极线相邻的第一字线布置成具有到第二互连的第二距离，第二距离为（4N + 1）倍于第一距离（N为1或更大的整数）。

公开(公告)号：US08093664B2

公开(公告)日：2012-01-10

申请号：US12359643

申请日：2009-01-26

申请人： Kenji Gomikawa ,  Mitsuhiro Noguchi

发明人： Kenji Gomikawa ,  Mitsuhiro Noguchi

IPC分类号： H01L29/66

CPC分类号： H01L29/7838 ,  H01L27/11526 ,  H01L27/11534

摘要： A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.

摘要翻译： 外围电路至少包括第一晶体管。 第一晶体管包括通过栅极绝缘膜形成在半导体层的表面上的栅电极。 具有第一杂质浓度的第一导电类型的沟道区形成在栅电极正下方和附近的半导体层的表面上。 第一导电类型的源极 - 漏极扩散区形成在半导体层的表面上以夹着栅电极，并且具有大于第一杂质浓度的第二杂质浓度。 第一导电类型的重叠区域形成在沟道区域和源极 - 漏极扩散区域重叠的栅电极正下方的半导体层的表面上。 重叠区域具有大于第二杂质浓度的第三杂质浓度。

公开(公告)号：US20110309422A1

公开(公告)日：2011-12-22

申请号：US13051516

申请日：2011-03-18

申请人： Masato ENDO ,  Mitsuhiro Noguchi

发明人： Masato ENDO ,  Mitsuhiro Noguchi

IPC分类号： H01L29/78

CPC分类号： H01L27/105 ,  H01L27/0629 ,  H01L27/11531 ,  H01L28/20

摘要： According to one embodiment, a semiconductor device includes a first resistance element including a first conductive material, an inter-gate insulation film formed on both ends of the first conductive material in a first direction, and a second conductive material formed above the first conductive material and configured to connect with the first conductive material via a first connection region from which the inter-gate insulation film is removed, and a second resistance element including a third conductive material, the inter-gate insulation film formed on both ends of the third conductive material in the first direction, and a fourth conductive material formed above the third conductive material and configured to connect with the third conductive material via a second connection region from which the inter-gate insulation film is removed, wherein a length of the second connection region is greater than a length of the first connection region in the first direction.

摘要翻译： 根据一个实施例，半导体器件包括第一电阻元件，第一电阻元件包括第一导电材料，在第一方向上形成在第一导电材料的两端上的栅极间绝缘膜和形成在第一导电材料上方的第二导电材料 并且被配置为经由去除所述栅极间绝缘膜的第一连接区域与所述第一导电材料连接，以及包括第三导电材料的第二电阻元件，所述栅极间绝缘膜形成在所述第三导电 材料在第一方向上形成，第四导电材料形成在第三导电材料之上，并被配置为经由去除栅间绝缘膜的第二连接区域与第三导电材料连接，其中第二连接区域 大于第一方向上的第一连接区域的长度。

公开(公告)号：US08044450B2

公开(公告)日：2011-10-25

申请号：US11174536

申请日：2005-07-06

申请人： Mitsuhiro Noguchi ,  Susumu Yoshikawa ,  Koichi Fukuda

发明人： Mitsuhiro Noguchi ,  Susumu Yoshikawa ,  Koichi Fukuda

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

摘要： A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in a self-aligned manner, and a second electrode, and the resistance element comprising a second isolation formed to isolate a second semiconductor area, a third insulator and a conductor layer in a self-aligned manner, and third and fourth electrodes formed on each end of the conductor layer via a fourth insulator, and connected with the conductor layer. The conductor layer or the third and fourth electrodes include the same material with the first or second electrode, respectively.

摘要翻译： 包括具有高电阻和高电阻精度的电阻元件和非易失性半导体存储元件的半导体器件通过包括非易失性半导体存储元件被合理地实现，所述非易失性半导体存储元件包括形成为隔离第一半导体区域的第一隔离，第一绝缘体 以及自对准方式的第一电极和第二电极，并且所述电阻元件包括形成为以自对准的方式隔离第二半导体区域，第三绝缘体和导体层的第二隔离，以及第三和 第四电极通过第四绝缘体形成在导体层的每个端部上，并与导体层连接。 导体层或第三和第四电极分别包括与第一或第二电极相同的材料。