公开(公告)号：US20240090215A1

公开(公告)日：2024-03-14

申请号：US17941534

申请日：2022-09-09

申请人： Winbond Electronics Corp.

发明人： Yuan-Huang WEI ,  Chien-Hsien WU ,  Hsiu-Han LIAO

IPC分类号： H01L27/11531 ,  H01L27/11521

CPC分类号： H01L27/11531 ,  H01L27/11521

摘要： The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.

公开(公告)号：US11653497B2

公开(公告)日：2023-05-16

申请号：US17498503

申请日：2021-10-11

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： H01L21/027 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  G11C8/10 ,  H01L21/02 ,  H01L27/11529 ,  H01L29/49

CPC分类号： H01L27/11582 ,  G11C8/10 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/495 ,  H01L29/4966

摘要： Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

公开(公告)号：US20180301372A1

公开(公告)日：2018-10-18

申请号：US15719170

申请日：2017-09-28

申请人： SK hynix Inc.

发明人： Yoo Hyun NOH

IPC分类号： H01L21/768 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11531 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11573 ,  H01L23/544 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66

CPC分类号： H01L21/76816 ,  H01L21/76877 ,  H01L22/12 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/544 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L2223/54426

摘要： Provided herein may be a method of manufacturing a semiconductor device. The method may include: forming a first stack in which a first pad region, a second pad region and first dummy region are successively defined; forming a second stack on the first stack; forming a first pad structure and a first reference pattern by patterning the second stack, the first pad structure being disposed on the first pad region and having a stepped shape, the first reference pattern being disposed on the first dummy region of the first stack; forming a first pad mask pattern on the first stack, the first pad mask pattern being aligned by measuring the distance from the first reference pattern thereto and covering the first and second pad regions; and forming a second pad structure having a stepped shape by patterning the second pad region while shrinking the first pad mask pattern.

公开(公告)号：US20180286882A1

公开(公告)日：2018-10-04

申请号：US15995407

申请日：2018-06-01

申请人： Toshiba Memory Corporation

发明人： Masaki TSUJI ,  Yoshiaki FUKUZUMI

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11597 ,  H01L27/11578 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11556

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11597 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

公开(公告)号：US10062704B2

公开(公告)日：2018-08-28

申请号：US15394592

申请日：2016-12-29

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Tzu Yin Chiu ,  Clifford Ian Drowley ,  Leong Tee Koh ,  Yu Lei Jiang ,  Da Qiang Yu

IPC分类号： H01L21/8234 ,  H01L27/11531 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11524 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66

CPC分类号： H01L27/11531 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/11524 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66825

摘要： A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.

公开(公告)号：US10056262B2

公开(公告)日：2018-08-21

申请号：US15479508

申请日：2017-04-05

申请人： SanDisk Technologies LLC

发明人： Keisuke Tsukamoto

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11526 ,  H01L27/11521

CPC分类号： H01L21/28052 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/7881

摘要： In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

公开(公告)号：US10020372B1

公开(公告)日：2018-07-10

申请号：US15496752

申请日：2017-04-25

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Khee Yong Lim ,  Kian Ming Tan ,  Fangxin Deng ,  Zhiqiang Teo ,  Xinshu Cai ,  Elgin Kiok Boone Quek ,  Fan Zhang

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/535 ,  H01L23/532 ,  H01L29/06

CPC分类号： H01L29/42328 ,  H01L21/02236 ,  H01L21/26513 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

摘要： A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.

公开(公告)号：US09929013B2

公开(公告)日：2018-03-27

申请号：US15402545

申请日：2017-01-10

申请人： Samsung Electronics Co., Ltd.

发明人： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC分类号： H01L21/033 ,  H01L21/027

CPC分类号： H01L21/0337 ,  H01L27/11531 ,  H01L27/11575

摘要： Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

公开(公告)号：US09871050B1

公开(公告)日：2018-01-16

申请号：US15232906

申请日：2016-08-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Ralf Richter ,  Sven Beyer ,  Jan Paul

IPC分类号： H01L29/788 ,  H01L27/11531 ,  H01L27/12 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11521

CPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1207 ,  H01L29/42328 ,  H01L29/42336

摘要： A method of manufacturing a flash memory device is provided including providing a silicon-on-insulator (SOI) substrate, in particular, a fully depleted silicon-on-insulator (FDSOI) substrate, comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and forming a memory device on the SOI substrate. Forming the flash memory device on the SOI substrate includes forming a flash transistor device and a read transistor device.

公开(公告)号：US20170373077A1

公开(公告)日：2017-12-28

申请号：US15701357

申请日：2017-09-11

申请人： Silicon Storage Technology, Inc.

发明人： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

IPC分类号： H01L27/11531 ,  H01L27/11524 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.