公开(公告)号：US08438365B2

公开(公告)日：2013-05-07

申请号：US11973895

申请日：2007-10-09

申请人： Timothy J. Southgate

发明人： Timothy J. Southgate

IPC分类号： G06F12/00

CPC分类号： G06F8/453 ,  G06F12/0802

摘要： A method of loading data into register files that correspond to respective execution units within a data-parallel processor. After receiving a first set of parameters that specify a subset of data within a first memory, the first set of parameters are compared to a plurality of sets of conditions that correspond to respective patterns of data. The first set of parameters is then converted to a second set of parameters in accordance with one of the sets of conditions satisfied by the first set of parameters. A sequence of memory addresses are generated based on the second set of parameters. Data is retrieved from locations within the first memory specified by the sequence of memory addresses and loaded into register files that correspond to respective execution units within a processor.

摘要翻译： 将数据加载到对应于数据并行处理器内的相应执行单元的寄存器文件中的方法。 在接收到指定第一存储器中的数据子集的第一组参数之后，将第一组参数与对应于各个数据模式的多组条件进行比较。 然后根据第一组参数满足的条件集合中的第一组参数将第一组参数转换为第二组参数。 基于第二组参数生成一系列存储器地址。 从由存储器地址序列指定的第一存储器内的位置检索数据，并将其加载到与处理器内各执行单元对应的寄存器文件中。

公开(公告)号：US08433830B2

公开(公告)日：2013-04-30

申请号：US13492878

申请日：2012-06-10

申请人： Peter Mattson ,  David Goodwin

发明人： Peter Mattson ,  David Goodwin

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

摘要翻译： 这里公开的是使用计算设备执行任务的技术。 启动第一个任务来执行第一个任务的操作。 创建表示对第一个任务的操作可访问的存储区域的缓冲区构造。 启动第二任务以执行第二任务的操作，其被配置为响应于从第一任务传送到第二任务的缓冲区构造来定时启动。

公开(公告)号：US20130241940A1

公开(公告)日：2013-09-19

申请号：US13886220

申请日：2013-05-02

申请人： CALOS FUND LIMITED LIABILITY COMPANY

发明人： Donald James Curry ,  Ujval J. Kapasi

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

摘要翻译： 在具有多个通道的单指令多数据（SIMD）处理器和专用于每个通道的本地存储器中，公开了处理图像的方法。 该方法包括将图像的连续光栅映射到连续的通道，使得连续的光栅组形成图像条，并且垂直的条带堆叠包括条带。 本地内存分配内存到图像条。 处理一系列功能以在流水线实施中在SIMD处理器上执行，使得流水线在多次迭代中循环图像的部分，并且在功能期间处理的中间数据被存储在本地存储器中。 通过在最左边的条形列中首先处理从顶部到底部的图像条，遍历与图像相关的数据，然后前进到每个相邻的未处理的条列。

公开(公告)号：US08412917B2

公开(公告)日：2013-04-02

申请号：US13237646

申请日：2011-09-20

申请人： Brucek Khailany ,  William James Dally ,  Ujval J. Kapasi ,  Jim Jian Lin

发明人： Brucek Khailany ,  William James Dally ,  Ujval J. Kapasi ,  Jim Jian Lin

IPC分类号： G06F9/00

CPC分类号： G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3891

摘要： Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer paths are dynamically determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. In addition, embodiments include an integrated-circuit processing device operable to execute operations in parallel, including the capability of providing confirmation information to potential source lanes, the confirmation information indicating whether the potential source lanes may send data to requested destination lanes during a data-transfer interval.

摘要翻译： 公开了用于动态地确定数据传送路径的方法和系统。 响应于便于执行并行操作的集成电路处理装置中的执行通道之间的数据传送的指令来动态地确定数据传送路径。 此外，实施例包括可并行执行操作的集成电路处理设备，包括向潜在源通道提供确认信息的能力，所述确认信息指示潜在源通道是否可以在数据通路期间向所请求的目的地通道发送数据， 传输间隔。

公开(公告)号：US20120254481A1

公开(公告)日：2012-10-04

申请号：US13492878

申请日：2012-06-10

申请人： Peter Mattson ,  David Goodwin

发明人： Peter Mattson ,  David Goodwin

IPC分类号： G06F13/28 ,  G06F5/00

CPC分类号： G06F13/28

摘要： Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

摘要翻译： 这里公开的是使用计算设备执行任务的技术。 启动第一个任务来执行第一个任务的操作。 创建表示第一个任务的操作可访问的存储区域的缓冲区构造。 启动第二任务以执行第二任务的操作，其被配置为响应于从第一任务传送到第二任务的缓冲区构造来定时启动。

公开(公告)号：US08321606B2

公开(公告)日：2012-11-27

申请号：US13281195

申请日：2011-10-25

申请人： Peter Mattson ,  David Goodwin

发明人： Peter Mattson ,  David Goodwin

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F12/0837 ,  G06F12/0888

摘要： Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.

摘要翻译： 这里公开的是使用包括与存储器的区域相关联的状态信息的缓冲器构造来管理对存储器的访问的技术。 所公开的技术有助于通过直接存储器访问操作来访问存储器区域，同时缓冲器构造的状态信息处于第一状态。 响应于第一指令，状态信息可以转换到第二状态。 所公开的技术还通过缓存操作促进对存储器区域的访问，同时公开了缓冲器构造的状态信息处于第二状态。 状态信息可以响应于第二指令而转变到第一状态。

公开(公告)号：US08219723B2

公开(公告)日：2012-07-10

申请号：US13275581

申请日：2011-10-18

申请人： Peter Mattson ,  David Goodwin

发明人： Peter Mattson ,  David Goodwin

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

摘要翻译： 这里公开的是使用计算设备执行任务的技术。 启动第一个任务来执行第一个任务的操作。 创建表示第一个任务的操作可访问的存储区域的缓冲区构造。 启动第二任务以执行第二任务的操作，其被配置为响应于从第一任务传送到第二任务的缓冲区构造来定时启动。

公开(公告)号：US08213509B2

公开(公告)日：2012-07-03

申请号：US11973889

申请日：2007-10-09

申请人： Ujval J. Kapasi ,  Amit Gulati ,  John Sievers

发明人： Ujval J. Kapasi ,  Amit Gulati ,  John Sievers

IPC分类号： H04N7/12

CPC分类号： H04N19/115 ,  H04N19/176 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/46 ,  H04N19/51 ,  H04N19/53 ,  H04N19/533 ,  H04N19/56 ,  H04N19/61

摘要： A method of estimating motion is disclosed. A first plurality of candidates is identified in a reference frame, wherein the total area occupied by the first plurality of candidates is substantially smaller than that of the reference frame. A first refinement search is then performed based, at least in part, on the first plurality of candidates. One or more best candidates are then identified based, at least in part, on the first refinement search. Finally, motion data is encoded based, at least in part, on the one or more best candidates.

摘要翻译： 公开了一种估计运动的方法。 在参考帧中识别第一多个候选，其中由第一多个候选占用的总面积显着小于参考帧的总面积。 然后，至少部分地基于第一多个候选进行第一细化搜索。 然后，至少部分地基于第一细化搜索来识别一个或多个最佳候选者。 最后，运动数据至少部分地基于一个或多个最佳候选者进行编码。

公开(公告)号：US08041852B1

公开(公告)日：2011-10-18

申请号：US12331357

申请日：2008-12-09

申请人： Peter Mattson ,  David Goodwin

发明人： Peter Mattson ,  David Goodwin

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A computer system is provided that utilizes a buffer construct to manage memory access operations to a region of memory. The buffer construct may correspond to a data item or structure that represents a region of memory. Each task may control the buffer construct exclusively of other tasks, so that the region of memory that is represented by the buffer construct is only available to the controlling task. Another task that requires access to the region of memory must wait until the controlling task makes the buffer construct available. The controlling task makes the buffer construct available only when DMA or other memory access operations that are in progress become complete. In this way, the buffer construct acts as a token that synchronizes each of the concurrent tasks execution and ensures mutually exclusive access to the common region of memory.

摘要翻译： 提供了一种使用缓冲器构造来管理到存储器区域的存储器访问操作的计算机系统。 缓冲区构造可以对应于表示存储器区域的数据项或结构。 每个任务可以专门控制其他任务的缓冲区构造，使得由缓冲区构造表示的内存区域仅对控制任务可用。 需要访问内存区域的另一个任务必须等到控制任务使缓冲区构造可用。 只有当正在进行的DMA或其他内存访问操作完成时，控制任务才使缓冲区构造可用。 以这种方式，缓冲区构造用作令牌，它同步每个并发任务执行，并确保对存储器的公共区域的互斥访问。

公开(公告)号：US08024553B2

公开(公告)日：2011-09-20

申请号：US12192813

申请日：2008-08-15

申请人： Brucek Khailany ,  William James Dally ,  Ujval J. Kapasi ,  Jim Jian Lin

发明人： Brucek Khailany ,  William James Dally ,  Ujval J. Kapasi ,  Jim Jian Lin

IPC分类号： G06F9/44 ,  G06F15/76

CPC分类号： G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3891

摘要： A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

摘要翻译： 一种具有多个执行通道的集成电路处理装置内的操作方法。 在接收到在执行通道之间交换数据的指令时，检查来自执行通道的相应请求，以确定在第一间隔期间可以将数据发送到执行通道的一个或多个其他执行通道的集合。 用信号通知执行通道集合内的每个执行通道，以指示执行通道可以向执行通道中的一个或其他执行通道发送数据。