Silicon Photoelectric Multiplier (Variants) and a Cell for Silicon Photoelectric Multiplier
    1.
    发明申请
    Silicon Photoelectric Multiplier (Variants) and a Cell for Silicon Photoelectric Multiplier 失效
    硅光电倍增器(变体)和硅光电倍增器单元

    公开(公告)号:US20080251692A1

    公开(公告)日:2008-10-16

    申请号:US11568646

    申请日:2005-05-05

    CPC classification number: H01L31/107 H01L27/144 H01L27/14643 H01L31/115

    Abstract: The invention relates to high-efficient light-recording detectors and can be used for nuclear and laser engineering, and in technical and medical tomography etc.The inventive silicon photoelectric multiplier (variant 1) comprising a p++ type conductivity substrate whose dope additive concentration ranges from 1018 to 1020 cm−3 and which consists of cells, each of which comprises a p-type conductivity epitaxial layer whose dope additive concentration is gradually changeable from 1018 to 1014 cm−3 and which is grown on the substrate, a p-type conductivity layer whose dope additive concentration ranges from 1015 to 1017 cm−3 and a n+ type conductivity layer whose dope additive concentration ranges from 1018 to 1020 cm−3, wherein a polysilicon resistor connecting the n+ type conductivity layer with a feed bar is arranged in each cell on a silicon oxide layer and separating elements are disposed between the cells. Said silicon photoelectric multiplier (variant 2) comprising a n-type conductivity substrate to which a p++-type conductivity whose dope additive concentration ranges from 1018-1020 cm−3 is applied and consists of cells, wherein in each cell a polysilicon resistor is placed on a silicon oxide layer and separating elements are disposed between the cells.

    Abstract translation: 本发明涉及高效的光记录检测器,可用于核和激光工程,以及技术和医学断层摄影等。本发明的硅光电倍增器(变型1)包括p ++型电导率基底,其掺杂剂浓度范围为 10×10〜10 20 cm -3,其由电池组成,每个电池包括p型导电外延层,其掺杂剂添加剂浓度 可以从10-18℃逐渐变化到10-14cm -3,并且在衬底上生长,p型导电层,其掺杂剂 浓度范围为10 15至10 17 cm -3,以及掺杂剂浓度范围为10 18 cm -3的n +型导电层, / SUP>至10 20 cm -3,其中将n +型导电层与进料棒连接的多晶硅电阻器布置在每个单元中的氧化硅1a上 分离元件设置在单元之间。 所述硅光电倍增器(变型2)包括n型导电性基板,掺杂浓度范围为10〜20±20cm的p ++型导电性 > -3 并且由单元组成,其中在每个单元中,多晶硅电阻器被放置在氧化硅层上,并且分离元件设置在单元之间。

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