公开(公告)号：US20140198838A1

公开(公告)日：2014-07-17

申请号：US14039773

申请日：2013-09-27

Applicant: Nathan R. Andrysco ,  Amit Puntambekar ,  Devadutta Ghat

Inventor： Nathan R. Andrysco ,  Amit Puntambekar ,  Devadutta Ghat

IPC: H04N7/26

CPC classification number: H04N19/167 ,  H04N19/115 ,  H04N19/12 ,  H04N19/172

Abstract: An apparatus may include a memory to store a video frame, a processor circuit and a selective encoding component for execution on the processor to perform selective encoding of the video frame, the selective encoding to classify the video frame into a primary object region and a background region, and encode the primary object region at a first quality level and the background region at a background quality level, the first quality level to comprise a higher quality level than the background quality level.

Abstract translation: 设备可以包括存储器，用于存储视频帧，处理器电路和选择性编码组件，用于在处理器上执行以执行视频帧的选择性编码，选择性编码以将视频帧分类为主要对象区域和背景 区域，并且以第一质量级别对主要对象区域进行编码，并且在背景质量级别对背景区域进行编码，第一质量水平包括比背景质量水平更高的质量水平。

公开(公告)号：US20140321532A1

公开(公告)日：2014-10-30

申请号：US13871478

申请日：2013-04-26

Applicant: DEVADUTTA GHAT ,  AMIT PUNTAMBEKAR ,  HIMANI D. TIDKE ,  VINUTHA RUMALE

Inventor： DEVADUTTA GHAT ,  AMIT PUNTAMBEKAR ,  HIMANI D. TIDKE ,  VINUTHA RUMALE

IPC: H04N19/40 ,  H04N19/124 ,  H04N19/115

CPC classification number: H04N19/124 ,  H04N19/40

Abstract: Various embodiments are generally directed to techniques to coordinate control of bitrates among multiple computing devices employed in parallel to transcode portions of a motion video. A device to coordinate parallel video transcoding includes a processor component; and a monitoring component for execution by the processor component to determine whether a total current bitrate remains within a target range of bitrates to transcode multiple segments of an original video data using multiple slave devices in parallel to generate a transcoded video data, the total current bitrate comprising a sum of current bitrates of video compression performed by the multiple slave devices in transcoding the multiple segments. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及协调对与运动视频的代码转换部分并行采用的多个计算设备之间的比特率的控制的技术。 协调并行视频代码转换的装置包括处理器组件; 以及用于由处理器组件执行的监视组件，用于确定总当前比特率是否保持在比特率的目标范围内，以使用并行的多个从设备对原始视频数据的多个段进行代码转换，以生成代码转换的视频数据，总的当前比特率 包括由多个从设备在对多个段进行代码转换时执行的视频压缩的当前比特率的总和。 描述和要求保护其他实施例。