System and method for cooperative execution of multiple branching instructions in a processor
    1.
    发明授权
    System and method for cooperative execution of multiple branching instructions in a processor 有权
    用于在处理器中协作执行多个分支指令的系统和方法

    公开(公告)号:US07299343B2

    公开(公告)日:2007-11-20

    申请号:US10256864

    申请日:2002-09-27

    IPC分类号: G06F9/44

    摘要: A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condition within the register. The system saves a result of each of the target instructions dependent upon the existence of the condition in the specified register during execution of the conditional execution instruction. When the conditional execution instruction specifies a first flag register, the system copies the flag bits in the first flag register to a corresponding second flag register, and saves a result of each of the target instructions dependent upon the specified condition in the first flag register during execution of the conditional execution instruction. A subsequent conditional execution instruction may then specify a condition in the second flag register in order to conditionally execute target instructions based on a previously existing condition.

    摘要翻译: 根据先前存在的条件有条件地执行指令的系统。 所公开的系统被配置为处理通常指定至少一个目标指令,处理器寄存器和寄存器内的条件的条件执行指令。 在执行条件执行指令期间,系统保存每个目标指令的结果,这取决于指定寄存器中条件的存在。 当条件执行指令指定第一标志寄存器时,系统将第一标志寄存器中的标志位复制到对应的第二标志寄存器,并且在第一标志寄存器期间将取决于指定条件的每个目标指令的结果保存在第一标志寄存器中 执行条件执行指令。 随后的条件执行指令可以指定第二标志寄存器中的条件,以便基于先前存在的条件有条件地执行目标指令。