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    Systems and methods for providing defect-tolerant logic devices
    1.
    发明授权
    Systems and methods for providing defect-tolerant logic devices 失效
    提供缺陷容错逻辑器件的系统和方法

    公开(公告)号：US07696774B2

    公开(公告)日：2010-04-13

    申请号：US12123972

    申请日：2008-05-20

    申请人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

    发明人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00392 ,  Y10T29/49002

    摘要： The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

    摘要翻译： 本发明描述了提供容错逻辑器件的系统和方法。 本发明的示例性实施例提供了一种缺陷容限逻辑器件，其包括多个CMOS栅极和包括在多个CMOS栅极内的至少一个缺陷CMOS栅极。 另外，如果至少一个有缺陷的CMOS栅极的P网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪NMOS晶体管。 此外，如果至少一个有缺陷的CMOS栅极的N网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪PMOS晶体管。

    SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES
    3.
    发明申请
    SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES 失效
    提供缺陷逻辑器件的系统和方法

    公开(公告)号：US20090289657A1

    公开(公告)日：2009-11-26

    申请号：US12123972

    申请日：2008-05-20

    申请人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

    发明人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

    IPC分类号： H03K19/003 ,  H01S4/00

    CPC分类号： H03K19/00392 ,  Y10T29/49002

    摘要： The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

    摘要翻译： 本发明描述了提供容错逻辑器件的系统和方法。 本发明的示例性实施例提供了一种缺陷容限逻辑器件，其包括多个CMOS栅极和包括在多个CMOS栅极内的至少一个缺陷CMOS栅极。 另外，如果至少一个有缺陷的CMOS栅极的P网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪NMOS晶体管。 此外，如果至少一个有缺陷的CMOS栅极的N网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪PMOS晶体管。

    System and method for estimating reliability of components for testing and quality optimization
    4.
    发明申请
    System and method for estimating reliability of components for testing and quality optimization 审中-公开
    用于估计组件可靠性的系统和方法，用于测试和质量优化

    公开(公告)号：US20080281541A1

    公开(公告)日：2008-11-13

    申请号：US12080159

    申请日：2008-03-31

    申请人： Adit D. Singh ,  Thomas S. Barnett

    发明人： Adit D. Singh ,  Thomas S. Barnett

    IPC分类号： G06F19/00

    CPC分类号： H01L22/20 ,  G01R31/287

    摘要： A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.

    摘要翻译： 一种用于确定电子部件的早期生命可靠性的系统和方法，包括基于对多个致命缺陷的初始确定来分类电子部件，并且基于该分类，估计电子部件中存在的潜在缺陷的概率， 旨在优化测试成本和产品质量。